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authorShinya Kuribayashi <shinya.kuribayashi.px@renesas.com>2010-06-17 20:36:13 +0900
committerRalf Baechle <ralf@linux-mips.org>2010-08-05 13:26:04 +0100
commit9e6f39698ac66e08017114a51600bf633becd011 (patch)
tree8541bf18a98af7cd8a7d5634b9d202a88d0df9b0 /arch/mips/emma
parenteebacda40f2f9818c92f61b2228c7888e1f4926c (diff)
downloadop-kernel-dev-9e6f39698ac66e08017114a51600bf633becd011.zip
op-kernel-dev-9e6f39698ac66e08017114a51600bf633becd011.tar.gz
MIPS: EMMA2RH: Remove EMMA2RH_CPU_CASCADE
Although all EMMAxxx SoCs can support IP2 and IP3 hardware interrupts, current EMMA2RH plat_irq_dispatch() supports IP2 only. We can make it configurable in the future, but for the time being, would like to make things explicitly allcated to IP2 in accordance with plat_irq_dispatch(). Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1388/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/emma')
-rw-r--r--arch/mips/emma/markeins/irq.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/emma/markeins/irq.c b/arch/mips/emma/markeins/irq.c
index 1d1c806..3a96799 100644
--- a/arch/mips/emma/markeins/irq.c
+++ b/arch/mips/emma/markeins/irq.c
@@ -301,7 +301,7 @@ void __init arch_init_irq(void)
/* setup cascade interrupts */
setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_SW_CASCADE, &irq_cascade);
setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_GPIO_CASCADE, &irq_cascade);
- setup_irq(MIPS_CPU_IRQ_BASE + CPU_EMMA2RH_CASCADE, &irq_cascade);
+ setup_irq(MIPS_CPU_IRQ_BASE + 2, &irq_cascade);
}
asmlinkage void plat_irq_dispatch(void)
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