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authorLinus Torvalds <torvalds@g5.osdl.org>2006-06-19 19:07:12 -0700
committerLinus Torvalds <torvalds@g5.osdl.org>2006-06-19 19:07:12 -0700
commit25f42b6af09e34c3f92107b36b5aa6edc2fdba2f (patch)
treee0977d906193eadeafebc442775491b844be79d5 /arch/mips/emma2rh/common/irq.c
parent4c84a39c8adba6bf2f829b217e78bfd61478191a (diff)
parent1723b4a34af85447684c9696af83929d2c1e8e6b (diff)
downloadop-kernel-dev-25f42b6af09e34c3f92107b36b5aa6edc2fdba2f.zip
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Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (51 commits) [MIPS] Make timer interrupt frequency configurable from kconfig. [MIPS] Correct HAL2 Kconfig description [MIPS] Fix R4K cache macro names [MIPS] Add Missing R4K Cache Macros to IP27 & IP32 [MIPS] Support for the RM9000-based Basler eXcite smart camera platform. [MIPS] Support for the R5500-based NEC EMMA2RH Mark-eins board [MIPS] Support SNI RM200C SNI in big endian mode and R5000 processors. [MIPS] SN: include asm/sn/types.h for nasid_t. [MIPS] Random fixes for sb1250 [MIPS] Fix bcm1480 compile [MIPS] Remove support for NEC DDB5476. [MIPS] Remove support for NEC DDB5074. [MIPS] Cleanup memory managment initialization. [MIPS] SN: Declare bridge_pci_ops. [MIPS] Remove unused function alloc_pci_controller. [MIPS] IP27: Extract pci_ops into separate file. [MIPS] IP27: Use symbolic constants instead of magic numbers. [MIPS] vr41xx: remove unnecessay items from vr41xx/Kconfig. [MIPS] IP27: Cleanup N/M mode configuration. [MIPS] IP27: Throw away old unused hacks. ...
Diffstat (limited to 'arch/mips/emma2rh/common/irq.c')
-rw-r--r--arch/mips/emma2rh/common/irq.c108
1 files changed, 108 insertions, 0 deletions
diff --git a/arch/mips/emma2rh/common/irq.c b/arch/mips/emma2rh/common/irq.c
new file mode 100644
index 0000000..b075281
--- /dev/null
+++ b/arch/mips/emma2rh/common/irq.c
@@ -0,0 +1,108 @@
+/*
+ * arch/mips/emma2rh/common/irq.c
+ * This file is common irq dispatcher.
+ *
+ * Copyright (C) NEC Electronics Corporation 2005-2006
+ *
+ * This file is based on the arch/mips/ddb5xxx/ddb5477/irq.c
+ *
+ * Copyright 2001 MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/types.h>
+
+#include <asm/i8259.h>
+#include <asm/system.h>
+#include <asm/mipsregs.h>
+#include <asm/debug.h>
+#include <asm/addrspace.h>
+#include <asm/bootinfo.h>
+
+#include <asm/emma2rh/emma2rh.h>
+
+/*
+ * the first level int-handler will jump here if it is a emma2rh irq
+ */
+asmlinkage void emma2rh_irq_dispatch(struct pt_regs *regs)
+{
+ u32 intStatus;
+ u32 bitmask;
+ u32 i;
+
+ intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_0)
+ & emma2rh_in32(EMMA2RH_BHIF_INT_EN_0);
+
+#ifdef EMMA2RH_SW_CASCADE
+ if (intStatus &
+ (1 << ((EMMA2RH_SW_CASCADE - EMMA2RH_IRQ_INT0) & (32 - 1)))) {
+ u32 swIntStatus;
+ swIntStatus = emma2rh_in32(EMMA2RH_BHIF_SW_INT)
+ & emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
+ for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
+ if (swIntStatus & bitmask) {
+ do_IRQ(EMMA2RH_SW_IRQ_BASE + i, regs);
+ return;
+ }
+ }
+ }
+#endif
+
+ for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
+ if (intStatus & bitmask) {
+ do_IRQ(EMMA2RH_IRQ_BASE + i, regs);
+ return;
+ }
+ }
+
+ intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_1)
+ & emma2rh_in32(EMMA2RH_BHIF_INT_EN_1);
+
+#ifdef EMMA2RH_GPIO_CASCADE
+ if (intStatus &
+ (1 << ((EMMA2RH_GPIO_CASCADE - EMMA2RH_IRQ_INT0) & (32 - 1)))) {
+ u32 gpioIntStatus;
+ gpioIntStatus = emma2rh_in32(EMMA2RH_GPIO_INT_ST)
+ & emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
+ for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
+ if (gpioIntStatus & bitmask) {
+ do_IRQ(EMMA2RH_GPIO_IRQ_BASE + i, regs);
+ return;
+ }
+ }
+ }
+#endif
+
+ for (i = 32, bitmask = 1; i < 64; i++, bitmask <<= 1) {
+ if (intStatus & bitmask) {
+ do_IRQ(EMMA2RH_IRQ_BASE + i, regs);
+ return;
+ }
+ }
+
+ intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_2)
+ & emma2rh_in32(EMMA2RH_BHIF_INT_EN_2);
+
+ for (i = 64, bitmask = 1; i < 96; i++, bitmask <<= 1) {
+ if (intStatus & bitmask) {
+ do_IRQ(EMMA2RH_IRQ_BASE + i, regs);
+ return;
+ }
+ }
+}
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