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authorAtsushi Nemoto <anemo@mba.ocn.ne.jp>2007-01-08 02:14:29 +0900
committerRalf Baechle <ralf@linux-mips.org>2007-02-06 16:53:08 +0000
commit97dcb82de6cc99a5669eb8e342efc24cceb1e77e (patch)
treee195fd57deda8d38652c746c04a7c374cdf951a0 /arch/mips/dec/setup.c
parentb6ec8f069bf202d2bd888aa9137b2cc3aad4c573 (diff)
downloadop-kernel-dev-97dcb82de6cc99a5669eb8e342efc24cceb1e77e.zip
op-kernel-dev-97dcb82de6cc99a5669eb8e342efc24cceb1e77e.tar.gz
[MIPS] Define MIPS_CPU_IRQ_BASE in generic header
The irq_base for {mips,rm7k,rm9k}_cpu_irq_init() are constant on all platforms and are same value on most platforms (0 or 16, depends on CONFIG_I8259). Define them in asm-mips/mach-generic/irq.h and make them customizable. This will save a few cycle on each CPU interrupt. A good side effect is removing some dependencies to MALTA in generic SMTC code. Although MIPS_CPU_IRQ_BASE is customizable, this patch changes irq mappings on DDB5477, EMMA2RH and MIPS_SIM, since really customizing them might cause some header dependency problem and there seems no good reason to customize it. So currently only VR41XX is using custom MIPS_CPU_IRQ_BASE value, which is 0 regardless of CONFIG_I8259. Testing this patch on those platforms is greatly appreciated. Thank you. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/dec/setup.c')
-rw-r--r--arch/mips/dec/setup.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/mips/dec/setup.c b/arch/mips/dec/setup.c
index d34032a..1058e2f 100644
--- a/arch/mips/dec/setup.c
+++ b/arch/mips/dec/setup.c
@@ -234,7 +234,7 @@ static void __init dec_init_kn01(void)
memcpy(&cpu_mask_nr_tbl, &kn01_cpu_mask_nr_tbl,
sizeof(kn01_cpu_mask_nr_tbl));
- mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
+ mips_cpu_irq_init();
} /* dec_init_kn01 */
@@ -309,7 +309,7 @@ static void __init dec_init_kn230(void)
memcpy(&cpu_mask_nr_tbl, &kn230_cpu_mask_nr_tbl,
sizeof(kn230_cpu_mask_nr_tbl));
- mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
+ mips_cpu_irq_init();
} /* dec_init_kn230 */
@@ -403,7 +403,7 @@ static void __init dec_init_kn02(void)
memcpy(&asic_mask_nr_tbl, &kn02_asic_mask_nr_tbl,
sizeof(kn02_asic_mask_nr_tbl));
- mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
+ mips_cpu_irq_init();
init_kn02_irqs(KN02_IRQ_BASE);
} /* dec_init_kn02 */
@@ -504,7 +504,7 @@ static void __init dec_init_kn02ba(void)
memcpy(&asic_mask_nr_tbl, &kn02ba_asic_mask_nr_tbl,
sizeof(kn02ba_asic_mask_nr_tbl));
- mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
+ mips_cpu_irq_init();
init_ioasic_irqs(IO_IRQ_BASE);
} /* dec_init_kn02ba */
@@ -601,7 +601,7 @@ static void __init dec_init_kn02ca(void)
memcpy(&asic_mask_nr_tbl, &kn02ca_asic_mask_nr_tbl,
sizeof(kn02ca_asic_mask_nr_tbl));
- mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
+ mips_cpu_irq_init();
init_ioasic_irqs(IO_IRQ_BASE);
} /* dec_init_kn02ca */
@@ -702,7 +702,7 @@ static void __init dec_init_kn03(void)
memcpy(&asic_mask_nr_tbl, &kn03_asic_mask_nr_tbl,
sizeof(kn03_asic_mask_nr_tbl));
- mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
+ mips_cpu_irq_init();
init_ioasic_irqs(IO_IRQ_BASE);
} /* dec_init_kn03 */
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