diff options
| author | Paul Mackerras <paulus@samba.org> | 2005-10-31 13:37:12 +1100 |
|---|---|---|
| committer | Paul Mackerras <paulus@samba.org> | 2005-10-31 13:37:12 +1100 |
| commit | 23fd07750a789a66fe88cf173d52a18f1a387da4 (patch) | |
| tree | 06fdd6df35fdb835abdaa9b754d62f6b84b97250 /arch/mips/dec/kn02-irq.c | |
| parent | bd787d438a59266af3c9f6351644c85ef1dd21fe (diff) | |
| parent | ed28f96ac1960f30f818374d65be71d2fdf811b0 (diff) | |
| download | op-kernel-dev-23fd07750a789a66fe88cf173d52a18f1a387da4.zip op-kernel-dev-23fd07750a789a66fe88cf173d52a18f1a387da4.tar.gz | |
Merge ../linux-2.6 by hand
Diffstat (limited to 'arch/mips/dec/kn02-irq.c')
| -rw-r--r-- | arch/mips/dec/kn02-irq.c | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/arch/mips/dec/kn02-irq.c b/arch/mips/dec/kn02-irq.c index e0bfcd1..898bed5 100644 --- a/arch/mips/dec/kn02-irq.c +++ b/arch/mips/dec/kn02-irq.c @@ -4,7 +4,7 @@ * DECstation 5000/200 (KN02) Control and Status Register * interrupts. * - * Copyright (c) 2002, 2003 Maciej W. Rozycki + * Copyright (c) 2002, 2003, 2005 Maciej W. Rozycki * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -37,7 +37,8 @@ static int kn02_irq_base; static inline void unmask_kn02_irq(unsigned int irq) { - volatile u32 *csr = (volatile u32 *)KN02_CSR_BASE; + volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + + KN02_CSR); cached_kn02_csr |= (1 << (irq - kn02_irq_base + 16)); *csr = cached_kn02_csr; @@ -45,7 +46,8 @@ static inline void unmask_kn02_irq(unsigned int irq) static inline void mask_kn02_irq(unsigned int irq) { - volatile u32 *csr = (volatile u32 *)KN02_CSR_BASE; + volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + + KN02_CSR); cached_kn02_csr &= ~(1 << (irq - kn02_irq_base + 16)); *csr = cached_kn02_csr; @@ -105,13 +107,14 @@ static struct hw_interrupt_type kn02_irq_type = { void __init init_kn02_irqs(int base) { - volatile u32 *csr = (volatile u32 *)KN02_CSR_BASE; + volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + + KN02_CSR); unsigned long flags; int i; /* Mask interrupts. */ spin_lock_irqsave(&kn02_lock, flags); - cached_kn02_csr &= ~KN03_CSR_IOINTEN; + cached_kn02_csr &= ~KN02_CSR_IOINTEN; *csr = cached_kn02_csr; iob(); spin_unlock_irqrestore(&kn02_lock, flags); |
