diff options
author | Andrew Bresticker <abrestic@chromium.org> | 2014-08-21 13:04:26 -0700 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2014-09-22 13:35:50 +0200 |
commit | 011eeece0bb2e1b65b2d2fd618067425e8ccdbb4 (patch) | |
tree | a38ac1e63ad8f5972494c342af9ef05597bd668c /arch/mips/boot/dts/rt2880.dtsi | |
parent | 36094619e419c306dc08d83f043bc9937cc63e03 (diff) | |
download | op-kernel-dev-011eeece0bb2e1b65b2d2fd618067425e8ccdbb4.zip op-kernel-dev-011eeece0bb2e1b65b2d2fd618067425e8ccdbb4.tar.gz |
MIPS: ralink: Move device-trees to arch/mips/boot/dts/
Move the Ralink device-trees to arch/mips/boot/dts/ and update the
Makefiles accordingly. A built-in device-tree is optional, so select
BUILTIN_DTB when it is requested.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: David Daney <david.daney@cavium.com>
Cc: John Crispin <blogic@openwrt.org>
Cc: Jayachandran C <jchandra@broadcom.com>
Cc: Qais Yousef <qais.yousef@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/7561/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/boot/dts/rt2880.dtsi')
-rw-r--r-- | arch/mips/boot/dts/rt2880.dtsi | 58 |
1 files changed, 58 insertions, 0 deletions
diff --git a/arch/mips/boot/dts/rt2880.dtsi b/arch/mips/boot/dts/rt2880.dtsi new file mode 100644 index 0000000..182afde --- /dev/null +++ b/arch/mips/boot/dts/rt2880.dtsi @@ -0,0 +1,58 @@ +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "ralink,rt2880-soc"; + + cpus { + cpu@0 { + compatible = "mips,mips4KEc"; + }; + }; + + cpuintc: cpuintc@0 { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + compatible = "mti,cpu-interrupt-controller"; + }; + + palmbus@300000 { + compatible = "palmbus"; + reg = <0x300000 0x200000>; + ranges = <0x0 0x300000 0x1FFFFF>; + + #address-cells = <1>; + #size-cells = <1>; + + sysc@0 { + compatible = "ralink,rt2880-sysc"; + reg = <0x0 0x100>; + }; + + intc: intc@200 { + compatible = "ralink,rt2880-intc"; + reg = <0x200 0x100>; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&cpuintc>; + interrupts = <2>; + }; + + memc@300 { + compatible = "ralink,rt2880-memc"; + reg = <0x300 0x100>; + }; + + uartlite@c00 { + compatible = "ralink,rt2880-uart", "ns16550a"; + reg = <0xc00 0x100>; + + interrupt-parent = <&intc>; + interrupts = <8>; + + reg-shift = <2>; + }; + }; +}; |