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authorthomas@koeller.dyndns.org <thomas@koeller.dyndns.org>2006-08-27 13:54:31 +0200
committerRalf Baechle <ralf@linux-mips.org>2006-09-27 13:37:50 +0100
commit0c68a9b6a7da0cc9095c117bea573f9058b00fff (patch)
tree985935dd47af45781a09089b34aaf238761e3b3c /arch/mips/basler
parent48712a96e31d11dce6dcb2a886894bd4d8b890f1 (diff)
downloadop-kernel-dev-0c68a9b6a7da0cc9095c117bea573f9058b00fff.zip
op-kernel-dev-0c68a9b6a7da0cc9095c117bea573f9058b00fff.tar.gz
[MIPS] Move excite_fpga.h to include/asm-mips/mach-excite
excite_fpga.h, like all platform headers, really belongs in the platform header directory. Signed-off-by: Thomas Koeller <thomas.koeller@baslerweb.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/basler')
-rw-r--r--arch/mips/basler/excite/excite_fpga.h80
1 files changed, 0 insertions, 80 deletions
diff --git a/arch/mips/basler/excite/excite_fpga.h b/arch/mips/basler/excite/excite_fpga.h
deleted file mode 100644
index 38fcda7..0000000
--- a/arch/mips/basler/excite/excite_fpga.h
+++ /dev/null
@@ -1,80 +0,0 @@
-#ifndef EXCITE_FPGA_H_INCLUDED
-#define EXCITE_FPGA_H_INCLUDED
-
-
-/**
- * Adress alignment of the individual FPGA bytes.
- * The address arrangement of the individual bytes of the FPGA is two
- * byte aligned at the embedded MK2 platform.
- */
-#ifdef EXCITE_CCI_FPGA_MK2
-typedef unsigned char excite_cci_fpga_align_t __attribute__ ((aligned(2)));
-#else
-typedef unsigned char excite_cci_fpga_align_t;
-#endif
-
-
-/**
- * Size of Dual Ported RAM.
- */
-#define EXCITE_DPR_SIZE 263
-
-
-/**
- * Size of Reserved Status Fields in Dual Ported RAM.
- */
-#define EXCITE_DPR_STATUS_SIZE 7
-
-
-
-/**
- * FPGA.
- * Hardware register layout of the FPGA interface. The FPGA must accessed
- * byte wise solely.
- * @see EXCITE_CCI_DPR_MK2
- */
-typedef struct excite_fpga {
-
- /**
- * Dual Ported RAM.
- */
- excite_cci_fpga_align_t dpr[EXCITE_DPR_SIZE];
-
- /**
- * Status.
- */
- excite_cci_fpga_align_t status[EXCITE_DPR_STATUS_SIZE];
-
-#ifdef EXCITE_CCI_FPGA_MK2
- /**
- * RM9000 Interrupt.
- * Write access initiates interrupt at the RM9000 (MIPS) processor of the eXcite.
- */
- excite_cci_fpga_align_t rm9k_int;
-#else
- /**
- * MK2 Interrupt.
- * Write access initiates interrupt at the ARM processor of the MK2.
- */
- excite_cci_fpga_align_t mk2_int;
-
- excite_cci_fpga_align_t gap[0x1000-0x10f];
-
- /**
- * IRQ Source/Acknowledge.
- */
- excite_cci_fpga_align_t rm9k_irq_src;
-
- /**
- * IRQ Mask.
- * Set bits enable the related interrupt.
- */
- excite_cci_fpga_align_t rm9k_irq_mask;
-#endif
-
-
-} excite_fpga;
-
-
-
-#endif /* ndef EXCITE_FPGA_H_INCLUDED */
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