summaryrefslogtreecommitdiffstats
path: root/arch/mips/alchemy
diff options
context:
space:
mode:
authorManuel Lauss <manuel.lauss@gmail.com>2015-01-29 16:06:42 +0100
committerRalf Baechle <ralf@linux-mips.org>2015-02-20 13:00:08 +0100
commit51f105d3074e8711698902ff89fcdc56193389ff (patch)
treedb846af7cef14e459e35666d36a8c6938c9e5ef4 /arch/mips/alchemy
parenta5770df09541f88021390375f324b25124675355 (diff)
downloadop-kernel-dev-51f105d3074e8711698902ff89fcdc56193389ff.zip
op-kernel-dev-51f105d3074e8711698902ff89fcdc56193389ff.tar.gz
MIPS: Alchemy: fix Au1000/Au1500 LRCLK calculation
The Au1000 and Au1500 calculate the LRCLK a bit differently than newer models: a single bit in MEM_STCFG0 selects if pclk is divided by 4 or 5. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/9148/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/alchemy')
-rw-r--r--arch/mips/alchemy/common/clock.c19
1 files changed, 14 insertions, 5 deletions
diff --git a/arch/mips/alchemy/common/clock.c b/arch/mips/alchemy/common/clock.c
index 48a9dfc..ade7337 100644
--- a/arch/mips/alchemy/common/clock.c
+++ b/arch/mips/alchemy/common/clock.c
@@ -315,17 +315,26 @@ static struct clk __init *alchemy_clk_setup_mem(const char *pn, int ct)
/* lrclk: external synchronous static bus clock ***********************/
-static struct clk __init *alchemy_clk_setup_lrclk(const char *pn)
+static struct clk __init *alchemy_clk_setup_lrclk(const char *pn, int t)
{
- /* MEM_STCFG0[15:13] = divisor.
+ /* Au1000, Au1500: MEM_STCFG0[11]: If bit is set, lrclk=pclk/5,
+ * otherwise lrclk=pclk/4.
+ * All other variants: MEM_STCFG0[15:13] = divisor.
* L/RCLK = periph_clk / (divisor + 1)
* On Au1000, Au1500, Au1100 it's called LCLK,
* on later models it's called RCLK, but it's the same thing.
*/
struct clk *c;
- unsigned long v = alchemy_rdsmem(AU1000_MEM_STCFG0) >> 13;
+ unsigned long v = alchemy_rdsmem(AU1000_MEM_STCFG0);
- v = (v & 7) + 1;
+ switch (t) {
+ case ALCHEMY_CPU_AU1000:
+ case ALCHEMY_CPU_AU1500:
+ v = 4 + ((v >> 11) & 1);
+ break;
+ default: /* all other models */
+ v = ((v >> 13) & 7) + 1;
+ }
c = clk_register_fixed_factor(NULL, ALCHEMY_LR_CLK,
pn, 0, 1, v);
if (!IS_ERR(c))
@@ -1060,7 +1069,7 @@ static int __init alchemy_clk_init(void)
ERRCK(c)
/* L/RCLK: external static bus clock for synchronous mode */
- c = alchemy_clk_setup_lrclk(ALCHEMY_PERIPH_CLK);
+ c = alchemy_clk_setup_lrclk(ALCHEMY_PERIPH_CLK, ctype);
ERRCK(c)
/* Frequency dividers 0-5 */
OpenPOWER on IntegriCloud