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authorManuel Lauss <manuel.lauss@googlemail.com>2011-05-08 10:42:17 +0200
committerRalf Baechle <ralf@linux-mips.org>2011-05-19 09:55:45 +0100
commit80130204b43ce9c3b50924e4c2d44e9f2881f8c3 (patch)
treeb136768ee20f226dbe0c55e1957f19e882784a5b /arch/mips/alchemy/xxs1500/board_setup.c
parentadcb86279f1e4d7a1a9f267b49441aecf4a5110a (diff)
downloadop-kernel-dev-80130204b43ce9c3b50924e4c2d44e9f2881f8c3.zip
op-kernel-dev-80130204b43ce9c3b50924e4c2d44e9f2881f8c3.tar.gz
MIPS: Alchemy: Rewrite UART setup and constants.
Detect CPU type at runtime and setup uarts accordingly; also clean up the uart base address mess in the process as far as possible. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Cc: Florian Fainelli <florian@openwrt.org> Cc: Wolfgang Grandegger <wg@grandegger.com> Patchwork: https://patchwork.linux-mips.org/patch/2352/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org
Diffstat (limited to 'arch/mips/alchemy/xxs1500/board_setup.c')
-rw-r--r--arch/mips/alchemy/xxs1500/board_setup.c11
1 files changed, 4 insertions, 7 deletions
diff --git a/arch/mips/alchemy/xxs1500/board_setup.c b/arch/mips/alchemy/xxs1500/board_setup.c
index febfb0fb..81e57fa 100644
--- a/arch/mips/alchemy/xxs1500/board_setup.c
+++ b/arch/mips/alchemy/xxs1500/board_setup.c
@@ -66,13 +66,10 @@ void __init board_setup(void)
au_writel(pin_func, SYS_PINFUNC);
/* Enable UART */
- au_writel(0x01, UART3_ADDR + UART_MOD_CNTRL); /* clock enable (CE) */
- mdelay(10);
- au_writel(0x03, UART3_ADDR + UART_MOD_CNTRL); /* CE and "enable" */
- mdelay(10);
-
- /* Enable DTR = USB power up */
- au_writel(0x01, UART3_ADDR + UART_MCR); /* UART_MCR_DTR is 0x01??? */
+ alchemy_uart_enable(AU1000_UART3_PHYS_ADDR);
+ /* Enable DTR (MCR bit 0) = USB power up */
+ __raw_writel(1, (void __iomem *)KSEG1ADDR(AU1000_UART3_PHYS_ADDR + 0x18));
+ wmb();
#ifdef CONFIG_PCI
#if defined(__MIPSEB__)
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