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| author | Paul Burton <paul.burton@imgtec.com> | 2014-01-15 10:31:53 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2014-03-26 23:00:12 +0100 |
| commit | 0ee958e102b62b418c2fb46c3439d4262067a5fc (patch) | |
| tree | e69192dc3112657cdde015ea8a43594a41a24d89 /arch/mips/Kconfig | |
| parent | b86c2247a20f5d8b6f2b3bd0dfd2c9c8c6908b5e (diff) | |
| download | op-kernel-dev-0ee958e102b62b418c2fb46c3439d4262067a5fc.zip op-kernel-dev-0ee958e102b62b418c2fb46c3439d4262067a5fc.tar.gz | |
MIPS: Coherent Processing System SMP implementation
This patch introduces a new SMP implementation for systems implementing
the MIPS Coherent Processing System architecture. The kernel will make
use of the Coherence Manager, Cluster Power Controller & Global
Interrupt Controller in order to detect, bring up & make use of other
cores in the system. SMTC is not supported, so only a single TC per VPE
in the system is used. That is, this option enables an SMVP style setup
but across multiple cores.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6362/
Patchwork: https://patchwork.linux-mips.org/patch/6611/
Patchwork: https://patchwork.linux-mips.org/patch/6651/
Patchwork: https://patchwork.linux-mips.org/patch/6652/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/Kconfig')
| -rw-r--r-- | arch/mips/Kconfig | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 2a9848e..a706779 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1887,6 +1887,7 @@ config MIPS_MT_SMTC bool "Use all TCs on all VPEs for SMP (DEPRECATED)" depends on CPU_MIPS32_R2 depends on SYS_SUPPORTS_MULTITHREADING + depends on !MIPS_CPS select CPU_MIPSR2_IRQ_VI select CPU_MIPSR2_IRQ_EI select MIPS_MT @@ -2003,6 +2004,23 @@ config MIPS_CMP help Enable Coherency Manager processor (CMP) support. +config MIPS_CPS + bool "MIPS Coherent Processing System support" + depends on SYS_SUPPORTS_MIPS_CPS + select MIPS_CM + select MIPS_CPC + select MIPS_GIC_IPI + select SMP + select SYNC_R4K if (CEVT_R4K || CSRC_R4K) + select SYS_SUPPORTS_SMP + select WEAK_ORDERING + help + Select this if you wish to run an SMP kernel across multiple cores + within a MIPS Coherent Processing System. When this option is + enabled the kernel will probe for other cores and boot them with + no external assistance. It is safe to enable this when hardware + support is unavailable. + config MIPS_GIC_IPI bool @@ -2191,6 +2209,9 @@ config SMP_UP config SYS_SUPPORTS_MIPS_CMP bool +config SYS_SUPPORTS_MIPS_CPS + bool + config SYS_SUPPORTS_SMP bool |
