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| author | Ralf Baechle <ralf@linux-mips.org> | 2007-10-11 23:46:09 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2007-10-11 23:46:09 +0100 |
| commit | ea5804015c0ce67741eb4b156a071fb4f415345f (patch) | |
| tree | bc4da66c0d9a531a17159b1cb001ad8e96d24487 /arch/mips/Kconfig | |
| parent | 7bcf7717b6a047c272410d0cd00213185fe6b99d (diff) | |
| download | op-kernel-dev-ea5804015c0ce67741eb4b156a071fb4f415345f.zip op-kernel-dev-ea5804015c0ce67741eb4b156a071fb4f415345f.tar.gz | |
[MIPS] Dyntick support for SMTC:
The kernel currently only supports broadcasting of the timer interrupt
from a single timer, not multicasting into two multicast groups of
processors. So the implemented mechanism for SMTC works by broadcasting
the cp0 compare interrupt on VPE 0 and ignoring it on any additional VPEs.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/Kconfig')
| -rw-r--r-- | arch/mips/Kconfig | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index ecce3aa..d8c9058 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1368,6 +1368,7 @@ config MIPS_MT_SMTC depends on CPU_MIPS32_R2 #depends on CPU_MIPS64_R2 # once there is hardware ... depends on SYS_SUPPORTS_MULTITHREADING + select GENERIC_CLOCKEVENTS_BROADCAST select CPU_MIPSR2_IRQ_VI select CPU_MIPSR2_IRQ_EI select CPU_MIPSR2_SRS @@ -1537,6 +1538,9 @@ config CPU_HAS_SYNC depends on !CPU_R3000 default y +config GENERIC_CLOCKEVENTS_BROADCAST + bool + # # Use the generic interrupt handling code in kernel/irq/: # |
