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| author | Paul Burton <paul.burton@imgtec.com> | 2014-01-15 10:31:59 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2014-03-26 23:09:08 +0100 |
| commit | a6ce202ead8c834913d068fd65cf29891478acde (patch) | |
| tree | 7a955a9b4490d65e4dc00b422ac7d0dc95bd6817 /arch/mips/Kconfig | |
| parent | 044505c78010942c740285e47561d2952743e830 (diff) | |
| download | op-kernel-dev-a6ce202ead8c834913d068fd65cf29891478acde.zip op-kernel-dev-a6ce202ead8c834913d068fd65cf29891478acde.tar.gz | |
MIPS: MIPS_CMP should depend upon !SMTC, not upon SMVP
Commit f55afb0969cc "MIPS: Clean up MIPS MT and CMP configuration
options." introduced a dependency upon MIPS_MT_SMP (ie. SMVP) for the
MIPS_CMP (ie. CMP framework support) Kconfig option. It did not specify
why, and that dependency is bogus. It is perfectly valid to have a
multi-core system with the YAMON bootloader but without MT support -
an example of this would be any multi-core proAptiv bitstream running on
a Malta. Forcing MT support to be enabled in a kernel for such a system
is incorrect. I suspect that the dependency was actually meant to
reflect the fact that YAMON will only bind 1 TC per VPE on an MT system,
and only describe those 1:1 TC:VPE pairs as CPUs through the AMON
interface. Thus an SMTC kernel makes little sense on a system using
MIPS_CMP, and the Kconfig dependencies should reflect that rather than
introducing the bogus SMVP dependency.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6368/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/Kconfig')
| -rw-r--r-- | arch/mips/Kconfig | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index bc681f0..d0b446e 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -2000,7 +2000,7 @@ config MIPS_VPE_APSP_API_MT config MIPS_CMP bool "MIPS CMP framework support" - depends on SYS_SUPPORTS_MIPS_CMP && MIPS_MT_SMP + depends on SYS_SUPPORTS_MIPS_CMP && !MIPS_MT_SMTC select MIPS_GIC_IPI select SYNC_R4K select WEAK_ORDERING |
