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authorGreg Ungerer <gerg@uclinux.org>2009-05-06 10:14:04 +1000
committerGreg Ungerer <gerg@uclinux.org>2009-09-16 09:43:47 +1000
commita3d9bf1dfdaf6f7df6c5340521dff1aafe39393f (patch)
tree874c35257c31857c33b358195f0ef1c535c2625b /arch/m68knommu
parentde4cbfb5994465e7c0f4cc545722b1144e8ba717 (diff)
downloadop-kernel-dev-a3d9bf1dfdaf6f7df6c5340521dff1aafe39393f.zip
op-kernel-dev-a3d9bf1dfdaf6f7df6c5340521dff1aafe39393f.tar.gz
m68knommu: remove unecessary interrupt level setting in ColdFire 520x setup
The new code for the interrupt controller in the ColdFire 520x takes care of all the interrupt controller setup. No manual config of the level registers (ICR) is required by the platform device setup code. So remove it. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68knommu')
-rw-r--r--arch/m68knommu/platform/520x/config.c9
1 files changed, 0 insertions, 9 deletions
diff --git a/arch/m68knommu/platform/520x/config.c b/arch/m68knommu/platform/520x/config.c
index 6a1fd74..92614de 100644
--- a/arch/m68knommu/platform/520x/config.c
+++ b/arch/m68knommu/platform/520x/config.c
@@ -81,15 +81,11 @@ static struct platform_device *m520x_devices[] __initdata = {
/***************************************************************************/
-#define INTC0 (MCF_MBAR + MCFICM_INTC0)
-
static void __init m520x_uart_init_line(int line, int irq)
{
u16 par;
u8 par2;
- writeb(0x03, INTC0 + MCFINTC_ICR0 + MCFINT_UART0 + line);
-
switch (line) {
case 0:
par = readw(MCF_IPSBAR + MCF_GPIO_PAR_UART);
@@ -128,11 +124,6 @@ static void __init m520x_fec_init(void)
{
u8 v;
- /* Unmask FEC interrupts at ColdFire interrupt controller */
- writeb(0x4, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0 + 36);
- writeb(0x4, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0 + 40);
- writeb(0x4, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0 + 42);
-
/* Set multi-function pins to ethernet mode */
v = readb(MCF_IPSBAR + MCF_GPIO_PAR_FEC);
writeb(v | 0xf0, MCF_IPSBAR + MCF_GPIO_PAR_FEC);
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