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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2011-01-18 08:05:20 -0800 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2011-01-18 08:05:20 -0800 |
| commit | 6a7f6ec9512970874fa9fc883ea44d77d0f287c2 (patch) | |
| tree | 2bce1665b5a9e81bdd95f6e34410bdf13c58350e /arch/m68knommu/platform/coldfire/head.S | |
| parent | c6fa63c659b3dd121f21afe7529f505505e79b23 (diff) | |
| parent | 4c65595ec506ff65c90b1d9fed17333005fa5eb5 (diff) | |
| download | op-kernel-dev-6a7f6ec9512970874fa9fc883ea44d77d0f287c2.zip op-kernel-dev-6a7f6ec9512970874fa9fc883ea44d77d0f287c2.tar.gz | |
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu: (25 commits)
m68knommu: fix broken setting of irq_chip and handler
m68knommu: switch to using -mcpu= flags for ColdFire targets
m68knommu: arch/m68knommu/Kconfig whitespace cleanup
m68knommu: create optimal separate instruction and data cache for ColdFire
m68knommu: support ColdFire caches that do copyback and write-through
m68knommu: support version 2 ColdFire split cache
m68knommu: make cache push code ColdFire generic
m68knommu: clean up ColdFire cache control code
m68knommu: move inclusion of ColdFire v4 cache registers
m68knommu: merge bit definitions for version 3 ColdFire cache controller
m68knommu: create bit definitions for the version 2 ColdFire cache controller
m68knommu: remove empty __iounmap() it is no used
m68knommu: remove kernel_map() code, it is not used
m68knommu: remove do_page_fault(), it is not used
m68knommu: use user stack pointer hardware on some ColdFire cores
m68knommu: remove command line printing DEBUG
m68knommu: remove fasthandler interrupt code
m68knommu: move UART addressing to part specific includes
m68knommu: fix clock rate value reported for ColdFire 54xx parts
m68knommu: move ColdFire CPU names into their headers
...
Diffstat (limited to 'arch/m68knommu/platform/coldfire/head.S')
| -rw-r--r-- | arch/m68knommu/platform/coldfire/head.S | 26 |
1 files changed, 21 insertions, 5 deletions
diff --git a/arch/m68knommu/platform/coldfire/head.S b/arch/m68knommu/platform/coldfire/head.S index 0b2d7c7..d597790 100644 --- a/arch/m68knommu/platform/coldfire/head.S +++ b/arch/m68knommu/platform/coldfire/head.S @@ -3,7 +3,7 @@ /* * head.S -- common startup code for ColdFire CPUs. * - * (C) Copyright 1999-2006, Greg Ungerer <gerg@snapgear.com>. + * (C) Copyright 1999-2010, Greg Ungerer <gerg@snapgear.com>. */ /*****************************************************************************/ @@ -13,7 +13,6 @@ #include <linux/init.h> #include <asm/asm-offsets.h> #include <asm/coldfire.h> -#include <asm/mcfcache.h> #include <asm/mcfsim.h> #include <asm/thread_info.h> @@ -173,10 +172,27 @@ _start: /* * Now that we know what the memory is, lets enable cache - * and get things moving. This is Coldfire CPU specific. + * and get things moving. This is Coldfire CPU specific. Not + * all version cores have identical cache register setup. But + * it is very similar. Define the exact settings in the headers + * then the code here is the same for all. */ - CACHE_ENABLE /* enable CPU cache */ - + movel #CACHE_INIT,%d0 /* invalidate whole cache */ + movec %d0,%CACR + nop + movel #ACR0_MODE,%d0 /* set RAM region for caching */ + movec %d0,%ACR0 + movel #ACR1_MODE,%d0 /* anything else to cache? */ + movec %d0,%ACR1 +#ifdef ACR2_MODE + movel #ACR2_MODE,%d0 + movec %d0,%ACR2 + movel #ACR3_MODE,%d0 + movec %d0,%ACR3 +#endif + movel #CACHE_MODE,%d0 /* enable cache */ + movec %d0,%CACR + nop #ifdef CONFIG_ROMFS_FS /* |
