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authorGreg Ungerer <gerg@uclinux.org>2012-09-18 15:38:15 +1000
committerGreg Ungerer <gerg@uclinux.org>2012-09-27 23:34:06 +1000
commit39dc5b7fcebe3cca65b775f743416107ec321e0b (patch)
tree38113cc1756c3132dd1b859970ee112392d4028f /arch/m68k
parent41e5be6a0e3bd0b54b7d2e60ba3225887286a45f (diff)
downloadop-kernel-dev-39dc5b7fcebe3cca65b775f743416107ec321e0b.zip
op-kernel-dev-39dc5b7fcebe3cca65b775f743416107ec321e0b.tar.gz
m68knommu: fix inconsistent formating in ColdFire 527x definitions
Fix tab broken address defines to be consistent with others in this file. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68k')
-rw-r--r--arch/m68k/include/asm/m527xsim.h34
1 files changed, 17 insertions, 17 deletions
diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h
index 6335e42..1bebbe7 100644
--- a/arch/m68k/include/asm/m527xsim.h
+++ b/arch/m68k/include/asm/m527xsim.h
@@ -184,15 +184,15 @@
/*
* Generic GPIO support
*/
-#define MCFGPIO_PODR MCFGPIO_PODR_ADDR
-#define MCFGPIO_PDDR MCFGPIO_PDDR_ADDR
-#define MCFGPIO_PPDR MCFGPIO_PPDSDR_ADDR
-#define MCFGPIO_SETR MCFGPIO_PPDSDR_ADDR
-#define MCFGPIO_CLRR MCFGPIO_PCLRR_ADDR
+#define MCFGPIO_PODR MCFGPIO_PODR_ADDR
+#define MCFGPIO_PDDR MCFGPIO_PDDR_ADDR
+#define MCFGPIO_PPDR MCFGPIO_PPDSDR_ADDR
+#define MCFGPIO_SETR MCFGPIO_PPDSDR_ADDR
+#define MCFGPIO_CLRR MCFGPIO_PCLRR_ADDR
-#define MCFGPIO_PIN_MAX 100
-#define MCFGPIO_IRQ_MAX 8
-#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
+#define MCFGPIO_PIN_MAX 100
+#define MCFGPIO_IRQ_MAX 8
+#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
/*
* Port Pin Assignment registers.
@@ -293,15 +293,15 @@
/*
* Generic GPIO support
*/
-#define MCFGPIO_PODR MCFGPIO_PODR_BUSCTL
-#define MCFGPIO_PDDR MCFGPIO_PDDR_BUSCTL
-#define MCFGPIO_PPDR MCFGPIO_PPDSDR_BUSCTL
-#define MCFGPIO_SETR MCFGPIO_PPDSDR_BUSCTL
-#define MCFGPIO_CLRR MCFGPIO_PCLRR_BUSCTL
-
-#define MCFGPIO_PIN_MAX 148
-#define MCFGPIO_IRQ_MAX 8
-#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
+#define MCFGPIO_PODR MCFGPIO_PODR_BUSCTL
+#define MCFGPIO_PDDR MCFGPIO_PDDR_BUSCTL
+#define MCFGPIO_PPDR MCFGPIO_PPDSDR_BUSCTL
+#define MCFGPIO_SETR MCFGPIO_PPDSDR_BUSCTL
+#define MCFGPIO_CLRR MCFGPIO_PCLRR_BUSCTL
+
+#define MCFGPIO_PIN_MAX 148
+#define MCFGPIO_IRQ_MAX 8
+#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
/*
* Port Pin Assignment registers.
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