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authorsfking@fdwdc.com <sfking@fdwdc.com>2009-06-19 18:11:04 -0700
committerGreg Ungerer <gerg@uclinux.org>2009-09-10 12:01:22 +1000
commita03ce7d9ef05e145ef706f99e68d5ffacf0ad325 (patch)
treef654f0374276f65f9d61f80204b81949d1845168 /arch/m68k
parentafde8560b4217338c17b7dbc9e9d7676c1b3a5ff (diff)
downloadop-kernel-dev-a03ce7d9ef05e145ef706f99e68d5ffacf0ad325.zip
op-kernel-dev-a03ce7d9ef05e145ef706f99e68d5ffacf0ad325.tar.gz
generic GPIO support for the Freescale Coldfire 523x.
Add support for the 523x. Signed-off-by: Steven King <sfking@fdwdc.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68k')
-rw-r--r--arch/m68k/include/asm/m523xsim.h77
1 files changed, 77 insertions, 0 deletions
diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h
index 55183b5d..a34894c 100644
--- a/arch/m68k/include/asm/m523xsim.h
+++ b/arch/m68k/include/asm/m523xsim.h
@@ -50,5 +50,82 @@
#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
+#define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000)
+#define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001)
+#define MCFGPIO_PODR_DATAL (MCF_IPSBAR + 0x100002)
+#define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 0x100003)
+#define MCFGPIO_PODR_BS (MCF_IPSBAR + 0x100004)
+#define MCFGPIO_PODR_CS (MCF_IPSBAR + 0x100005)
+#define MCFGPIO_PODR_SDRAM (MCF_IPSBAR + 0x100006)
+#define MCFGPIO_PODR_FECI2C (MCF_IPSBAR + 0x100007)
+#define MCFGPIO_PODR_UARTH (MCF_IPSBAR + 0x100008)
+#define MCFGPIO_PODR_UARTL (MCF_IPSBAR + 0x100009)
+#define MCFGPIO_PODR_QSPI (MCF_IPSBAR + 0x10000A)
+#define MCFGPIO_PODR_TIMER (MCF_IPSBAR + 0x10000B)
+#define MCFGPIO_PODR_ETPU (MCF_IPSBAR + 0x10000C)
+
+#define MCFGPIO_PDDR_ADDR (MCF_IPSBAR + 0x100010)
+#define MCFGPIO_PDDR_DATAH (MCF_IPSBAR + 0x100011)
+#define MCFGPIO_PDDR_DATAL (MCF_IPSBAR + 0x100012)
+#define MCFGPIO_PDDR_BUSCTL (MCF_IPSBAR + 0x100013)
+#define MCFGPIO_PDDR_BS (MCF_IPSBAR + 0x100014)
+#define MCFGPIO_PDDR_CS (MCF_IPSBAR + 0x100015)
+#define MCFGPIO_PDDR_SDRAM (MCF_IPSBAR + 0x100016)
+#define MCFGPIO_PDDR_FECI2C (MCF_IPSBAR + 0x100017)
+#define MCFGPIO_PDDR_UARTH (MCF_IPSBAR + 0x100018)
+#define MCFGPIO_PDDR_UARTL (MCF_IPSBAR + 0x100019)
+#define MCFGPIO_PDDR_QSPI (MCF_IPSBAR + 0x10001A)
+#define MCFGPIO_PDDR_TIMER (MCF_IPSBAR + 0x10001B)
+#define MCFGPIO_PDDR_ETPU (MCF_IPSBAR + 0x10001C)
+
+#define MCFGPIO_PPDSDR_ADDR (MCF_IPSBAR + 0x100020)
+#define MCFGPIO_PPDSDR_DATAH (MCF_IPSBAR + 0x100021)
+#define MCFGPIO_PPDSDR_DATAL (MCF_IPSBAR + 0x100022)
+#define MCFGPIO_PPDSDR_BUSCTL (MCF_IPSBAR + 0x100023)
+#define MCFGPIO_PPDSDR_BS (MCF_IPSBAR + 0x100024)
+#define MCFGPIO_PPDSDR_CS (MCF_IPSBAR + 0x100025)
+#define MCFGPIO_PPDSDR_SDRAM (MCF_IPSBAR + 0x100026)
+#define MCFGPIO_PPDSDR_FECI2C (MCF_IPSBAR + 0x100027)
+#define MCFGPIO_PPDSDR_UARTH (MCF_IPSBAR + 0x100028)
+#define MCFGPIO_PPDSDR_UARTL (MCF_IPSBAR + 0x100029)
+#define MCFGPIO_PPDSDR_QSPI (MCF_IPSBAR + 0x10002A)
+#define MCFGPIO_PPDSDR_TIMER (MCF_IPSBAR + 0x10002B)
+#define MCFGPIO_PPDSDR_ETPU (MCF_IPSBAR + 0x10002C)
+
+#define MCFGPIO_PCLRR_ADDR (MCF_IPSBAR + 0x100030)
+#define MCFGPIO_PCLRR_DATAH (MCF_IPSBAR + 0x100031)
+#define MCFGPIO_PCLRR_DATAL (MCF_IPSBAR + 0x100032)
+#define MCFGPIO_PCLRR_BUSCTL (MCF_IPSBAR + 0x100033)
+#define MCFGPIO_PCLRR_BS (MCF_IPSBAR + 0x100034)
+#define MCFGPIO_PCLRR_CS (MCF_IPSBAR + 0x100035)
+#define MCFGPIO_PCLRR_SDRAM (MCF_IPSBAR + 0x100036)
+#define MCFGPIO_PCLRR_FECI2C (MCF_IPSBAR + 0x100037)
+#define MCFGPIO_PCLRR_UARTH (MCF_IPSBAR + 0x100038)
+#define MCFGPIO_PCLRR_UARTL (MCF_IPSBAR + 0x100039)
+#define MCFGPIO_PCLRR_QSPI (MCF_IPSBAR + 0x10003A)
+#define MCFGPIO_PCLRR_TIMER (MCF_IPSBAR + 0x10003B)
+#define MCFGPIO_PCLRR_ETPU (MCF_IPSBAR + 0x10003C)
+
+/*
+ * EPort
+ */
+
+#define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002)
+#define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004)
+#define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005)
+
+/*
+ * Generic GPIO support
+ */
+#define MCFGPIO_PODR MCFGPIO_PODR_ADDR
+#define MCFGPIO_PDDR MCFGPIO_PDDR_ADDR
+#define MCFGPIO_PPDR MCFGPIO_PPDSDR_ADDR
+#define MCFGPIO_SETR MCFGPIO_PPDSDR_ADDR
+#define MCFGPIO_CLRR MCFGPIO_PCLRR_ADDR
+
+#define MCFGPIO_PIN_MAX 107
+#define MCFGPIO_IRQ_MAX 8
+#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
+
/****************************************************************************/
#endif /* m523xsim_h */
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