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authorGreg Ungerer <gerg@uclinux.org>2012-09-17 12:07:21 +1000
committerGreg Ungerer <gerg@uclinux.org>2012-09-27 23:33:56 +1000
commitf821e349cf2539bc7752652ef7b60030c1fc49fb (patch)
tree31f0e529b2ab4ca65cfcc39c187d74577a835a19 /arch/m68k/platform
parent8a415c4be5401f94d7be075682b8c0f43440329a (diff)
downloadop-kernel-dev-f821e349cf2539bc7752652ef7b60030c1fc49fb.zip
op-kernel-dev-f821e349cf2539bc7752652ef7b60030c1fc49fb.tar.gz
m68knommu: remove address offsets relative to IPSBAR for ColdFire 527x
Remove the last address definitions relative to the IPSBAR peripheral region for the ColdFire 527x family. This involved cleaning up some magic numbers used in the code part, and making them proper register definitions in the 527x specific header. This is part of the process of cleaning up the ColdFire register definitions to make them consistently use absolute addresses for the primary registers. This will reduce the occasional bugs caused by inconsistent definition of the register addresses. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68k/platform')
-rw-r--r--arch/m68k/platform/coldfire/m527x.c24
1 files changed, 12 insertions, 12 deletions
diff --git a/arch/m68k/platform/coldfire/m527x.c b/arch/m68k/platform/coldfire/m527x.c
index b3cb378..1431ba0 100644
--- a/arch/m68k/platform/coldfire/m527x.c
+++ b/arch/m68k/platform/coldfire/m527x.c
@@ -53,9 +53,9 @@ static void __init m527x_uarts_init(void)
/*
* External Pin Mask Setting & Enable External Pin for Interface
*/
- sepmask = readw(MCF_IPSBAR + MCF_GPIO_PAR_UART);
+ sepmask = readw(MCFGPIO_PAR_UART);
sepmask |= UART0_ENABLE_MASK | UART1_ENABLE_MASK | UART2_ENABLE_MASK;
- writew(sepmask, MCF_IPSBAR + MCF_GPIO_PAR_UART);
+ writew(sepmask, MCFGPIO_PAR_UART);
}
/***************************************************************************/
@@ -67,19 +67,19 @@ static void __init m527x_fec_init(void)
/* Set multi-function pins to ethernet mode for fec0 */
#if defined(CONFIG_M5271)
- v = readb(MCF_IPSBAR + 0x100047);
- writeb(v | 0xf0, MCF_IPSBAR + 0x100047);
+ v = readb(MCFGPIO_PAR_FECI2C);
+ writeb(v | 0xf0, MCFGPIO_PAR_FECI2C);
#else
- par = readw(MCF_IPSBAR + 0x100082);
- writew(par | 0xf00, MCF_IPSBAR + 0x100082);
- v = readb(MCF_IPSBAR + 0x100078);
- writeb(v | 0xc0, MCF_IPSBAR + 0x100078);
+ par = readw(MCFGPIO_PAR_FECI2C);
+ writew(par | 0xf00, MCFGPIO_PAR_FECI2C);
+ v = readb(MCFGPIO_PAR_FEC0HL);
+ writeb(v | 0xc0, MCFGPIO_PAR_FEC0HL);
/* Set multi-function pins to ethernet mode for fec1 */
- par = readw(MCF_IPSBAR + 0x100082);
- writew(par | 0xa0, MCF_IPSBAR + 0x100082);
- v = readb(MCF_IPSBAR + 0x100079);
- writeb(v | 0xc0, MCF_IPSBAR + 0x100079);
+ par = readw(MCFGPIO_PAR_FECI2C);
+ writew(par | 0xa0, MCFGPIO_PAR_FECI2C);
+ v = readb(MCFGPIO_PAR_FEC1HL);
+ writeb(v | 0xc0, MCFGPIO_PAR_FEC1HL);
#endif
}
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