diff options
| author | sfking@fdwdc.com <sfking@fdwdc.com> | 2009-06-19 18:11:07 -0700 |
|---|---|---|
| committer | Greg Ungerer <gerg@uclinux.org> | 2009-09-10 12:01:23 +1000 |
| commit | 316f2c483c32e9385329303258d12e6e33892af5 (patch) | |
| tree | dee9cb00d46899a392a62ad3c1c9f003cd631326 /arch/m68k/include | |
| parent | f1554da34f11518bde33776c292c1b58fc20f073 (diff) | |
| download | op-kernel-dev-316f2c483c32e9385329303258d12e6e33892af5.zip op-kernel-dev-316f2c483c32e9385329303258d12e6e33892af5.tar.gz | |
generic GPIO support for the Freescale Coldfire 5272.
Add support for the 5272.
Signed-off-by: Steven King <sfking@fdwdc.com>
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68k/include')
| -rw-r--r-- | arch/m68k/include/asm/m5272sim.h | 24 |
1 files changed, 15 insertions, 9 deletions
diff --git a/arch/m68k/include/asm/m5272sim.h b/arch/m68k/include/asm/m5272sim.h index 6217edc..0665ba1 100644 --- a/arch/m68k/include/asm/m5272sim.h +++ b/arch/m68k/include/asm/m5272sim.h @@ -63,16 +63,22 @@ #define MCFSIM_DCMR1 0x5c /* DRAM 1 Mask reg (r/w) */ #define MCFSIM_DCCR1 0x63 /* DRAM 1 Control reg (r/w) */ -#define MCFSIM_PACNT 0x80 /* Port A Control (r/w) */ -#define MCFSIM_PADDR 0x84 /* Port A Direction (r/w) */ -#define MCFSIM_PADAT 0x86 /* Port A Data (r/w) */ -#define MCFSIM_PBCNT 0x88 /* Port B Control (r/w) */ -#define MCFSIM_PBDDR 0x8c /* Port B Direction (r/w) */ -#define MCFSIM_PBDAT 0x8e /* Port B Data (r/w) */ -#define MCFSIM_PCDDR 0x94 /* Port C Direction (r/w) */ -#define MCFSIM_PCDAT 0x96 /* Port C Data (r/w) */ -#define MCFSIM_PDCNT 0x98 /* Port D Control (r/w) */ +#define MCFSIM_PACNT (MCF_MBAR + 0x80) /* Port A Control (r/w) */ +#define MCFSIM_PADDR (MCF_MBAR + 0x84) /* Port A Direction (r/w) */ +#define MCFSIM_PADAT (MCF_MBAR + 0x86) /* Port A Data (r/w) */ +#define MCFSIM_PBCNT (MCF_MBAR + 0x88) /* Port B Control (r/w) */ +#define MCFSIM_PBDDR (MCF_MBAR + 0x8c) /* Port B Direction (r/w) */ +#define MCFSIM_PBDAT (MCF_MBAR + 0x8e) /* Port B Data (r/w) */ +#define MCFSIM_PCDDR (MCF_MBAR + 0x94) /* Port C Direction (r/w) */ +#define MCFSIM_PCDAT (MCF_MBAR + 0x96) /* Port C Data (r/w) */ +#define MCFSIM_PDCNT (MCF_MBAR + 0x98) /* Port D Control (r/w) */ +/* + * Generic GPIO support + */ +#define MCFGPIO_PIN_MAX 48 +#define MCFGPIO_IRQ_MAX -1 +#define MCFGPIO_IRQ_VECBASE -1 /****************************************************************************/ #endif /* m5272sim_h */ |
