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| author | Greg Ungerer <gerg@uclinux.org> | 2010-11-09 13:35:55 +1000 |
|---|---|---|
| committer | Greg Ungerer <gerg@uclinux.org> | 2011-01-05 15:19:18 +1000 |
| commit | 8ce877a8eb8293b5b2c07f259d694026b0f519e4 (patch) | |
| tree | d478523ee8bec4ecc638c9f9a35816fc12aaa37f /arch/m68k/include/asm/m54xxacr.h | |
| parent | 3d461401eb5e3a8c471e92500aebd6c115273fba (diff) | |
| download | op-kernel-dev-8ce877a8eb8293b5b2c07f259d694026b0f519e4.zip op-kernel-dev-8ce877a8eb8293b5b2c07f259d694026b0f519e4.tar.gz | |
m68knommu: clean up ColdFire cache control code
The cache control code for the ColdFire CPU's is a big ugly mess
of "#ifdef"ery liberally coated with bit constants. Clean it up.
The cache controllers in the various ColdFire parts are actually quite
similar. Just differing in some bit flags and options supported. Using
the header defines now in place it is pretty easy to factor out the
small differences and use common setup and flush/invalidate code.
I have preserved the cache setups as they where in the old code
(except where obviously wrong - like in the case of the 5249). Following
from this it should be easy now to extend the possible setups used on
the CACHE controllers that support split cacheing or copy-back or
write through options.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68k/include/asm/m54xxacr.h')
| -rw-r--r-- | arch/m68k/include/asm/m54xxacr.h | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/arch/m68k/include/asm/m54xxacr.h b/arch/m68k/include/asm/m54xxacr.h index 12209c6..3c81a7a 100644 --- a/arch/m68k/include/asm/m54xxacr.h +++ b/arch/m68k/include/asm/m54xxacr.h @@ -73,11 +73,16 @@ #else #define CACHE_MODE (CACR_DEC+CACR_DESB+CACR_DDCM_P+CACR_BEC+CACR_IEC+CACR_EUSP) #endif - #define DATA_CACHE_MODE (ACR_ENABLE+ACR_ANY+ACR_CM_WT) - #define INSN_CACHE_MODE (ACR_ENABLE+ACR_ANY) +#define CACHE_INIT (CACR_DCINVA+CACR_BCINVA+CACR_ICINVA) +#define CACHE_INVALIDATE (CACHE_MODE+CACR_DCINVA+CACR_BCINVA+CACR_ICINVA) +#define ACR0_MODE (0x000f0000+DATA_CACHE_MODE) +#define ACR1_MODE 0 +#define ACR2_MODE (0x000f0000+INSN_CACHE_MODE) +#define ACR3_MODE 0 + #ifndef __ASSEMBLY__ #if ((DATA_CACHE_MODE & ACR_CM) == ACR_CM_WT) @@ -112,7 +117,7 @@ static inline void __m54xx_flush_cache_all(void) : "i" (CACHE_LINE_SIZE), "i" (DCACHE_SIZE / CACHE_WAYS), "i" (CACHE_WAYS), - "i" (CACHE_MODE|CACR_DCINVA|CACR_BCINVA|CACR_ICINVA) + "i" (CACHE_INVALIDATE) : "d0", "a0" ); } |
