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author | Greg Ungerer <gerg@uclinux.org> | 2010-11-09 10:40:44 +1000 |
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committer | Greg Ungerer <gerg@uclinux.org> | 2011-01-05 15:19:18 +1000 |
commit | 3d461401eb5e3a8c471e92500aebd6c115273fba (patch) | |
tree | 9b8df3b3afb8f358851527db5c73b40dfc65228d /arch/m68k/include/asm/m5407sim.h | |
parent | 278c2cbd59371bc8905d83b7cc3aa0bbe69c00f1 (diff) | |
download | op-kernel-dev-3d461401eb5e3a8c471e92500aebd6c115273fba.zip op-kernel-dev-3d461401eb5e3a8c471e92500aebd6c115273fba.tar.gz |
m68knommu: move inclusion of ColdFire v4 cache registers
Move the inclusion of the version 4 cache controller registers so that
it is with all the other register bit flag definitions. This makes it
consistent with the other version core inclusion points, and means we
don't need "#ifdef"ery in odd-ball places for these definitions.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68k/include/asm/m5407sim.h')
-rw-r--r-- | arch/m68k/include/asm/m5407sim.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/m68k/include/asm/m5407sim.h b/arch/m68k/include/asm/m5407sim.h index ddfff88..75f5c28 100644 --- a/arch/m68k/include/asm/m5407sim.h +++ b/arch/m68k/include/asm/m5407sim.h @@ -17,6 +17,8 @@ #define CPU_NAME "COLDFIRE(m5407)" #define CPU_INSTR_PER_JIFFY 3 +#include <asm/m54xxacr.h> + /* * Define the 5407 SIM register set addresses. */ |