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| author | Greg Ungerer <gerg@uclinux.org> | 2011-12-24 12:44:45 +1000 |
|---|---|---|
| committer | Greg Ungerer <gerg@uclinux.org> | 2012-03-05 09:43:09 +1000 |
| commit | ed8a2798f6cff0dc68ca7d5800279525aa310fd0 (patch) | |
| tree | 9ba7fb53f2ef3c64eb2877272c3abb3d019d56c2 /arch/m68k/include/asm/m532xsim.h | |
| parent | 3b2039b26619745a736b896caf8df05a2a15df3a (diff) | |
| download | op-kernel-dev-ed8a2798f6cff0dc68ca7d5800279525aa310fd0.zip op-kernel-dev-ed8a2798f6cff0dc68ca7d5800279525aa310fd0.tar.gz | |
m68knommu: make 532x QSPI platform addressing consistent
If we make all QSPI (SPI protocol) addressing consistent across all ColdFire
family members then we will be able to remove the duplicated plaform data
and code and use a single setup for all.
So modify the ColdFire 532x QSPI addressing so that:
. base addresses are absolute (not relative to MBAR peripheral register)
. use a common name for IRQs used
. move chip select definitions (CS) to appropriate header
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68k/include/asm/m532xsim.h')
| -rw-r--r-- | arch/m68k/include/asm/m532xsim.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/m68k/include/asm/m532xsim.h b/arch/m68k/include/asm/m532xsim.h index f1c4fa8..29b66e2 100644 --- a/arch/m68k/include/asm/m532xsim.h +++ b/arch/m68k/include/asm/m532xsim.h @@ -36,6 +36,8 @@ #define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0) #define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0) +#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) + #define MCF_WTM_WCR MCF_REG16(0xFC098000) /* @@ -104,6 +106,16 @@ #define MCFFEC_SIZE0 0x800 /* Size of FEC0 region */ /* + * QSPI module. + */ +#define MCFQSPI_BASE 0xFC058000 /* Base address of QSPI */ +#define MCFQSPI_SIZE 0x40 /* Size of QSPI region */ + +#define MCFQSPI_CS0 84 +#define MCFQSPI_CS1 85 +#define MCFQSPI_CS2 86 + +/* * Timer module. */ #define MCFTIMER_BASE1 0xFC070000 /* Base address of TIMER1 */ |
