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authorGreg Ungerer <gerg@uclinux.org>2010-11-09 10:12:29 +1000
committerGreg Ungerer <gerg@uclinux.org>2011-01-05 15:19:18 +1000
commita12cf0a8c6e2763ac865aa31f296557e07432b8a (patch)
tree5b44bfe7aca132e1a3f0cd2bd7bbe2291b56a663 /arch/m68k/include/asm/m520xsim.h
parent63e83c8a52031555b1e724f98a33f1838dee6345 (diff)
downloadop-kernel-dev-a12cf0a8c6e2763ac865aa31f296557e07432b8a.zip
op-kernel-dev-a12cf0a8c6e2763ac865aa31f296557e07432b8a.tar.gz
m68knommu: create bit definitions for the version 2 ColdFire cache controller
The version 2 ColdFire CPU based cores all contain a similar cache controller unit. Create a set of bit flag definitions for the supporting registers. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68k/include/asm/m520xsim.h')
-rw-r--r--arch/m68k/include/asm/m520xsim.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h
index 8cd8bce..88ed823 100644
--- a/arch/m68k/include/asm/m520xsim.h
+++ b/arch/m68k/include/asm/m520xsim.h
@@ -14,6 +14,8 @@
#define CPU_NAME "COLDFIRE(m520x)"
#define CPU_INSTR_PER_JIFFY 3
+#include <asm/m52xxacr.h>
+
/*
* Define the 520x SIM register set addresses.
*/
@@ -57,6 +59,9 @@
#define MCFSIM_SDCS0 0x000a8110 /* SDRAM Chip Select 0 Configuration */
#define MCFSIM_SDCS1 0x000a8114 /* SDRAM Chip Select 1 Configuration */
+/*
+ * EPORT and GPIO registers.
+ */
#define MCFEPORT_EPDDR 0xFC088002
#define MCFEPORT_EPDR 0xFC088004
#define MCFEPORT_EPPDR 0xFC088005
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