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author | Hirokazu Takata <takata@linux-m32r.org> | 2006-01-06 00:18:41 -0800 |
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committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-01-06 08:33:43 -0800 |
commit | 9287d95ea194abf32fab24c6909f8ea55ab0292f (patch) | |
tree | 4c00a6866d1da4fac5b5ca3bdb86eb2170a3fbf4 /arch/m32r/kernel/time.c | |
parent | 60c83c77c4a6a399d55e4f9ad156bccdfe51c96b (diff) | |
download | op-kernel-dev-9287d95ea194abf32fab24c6909f8ea55ab0292f.zip op-kernel-dev-9287d95ea194abf32fab24c6909f8ea55ab0292f.tar.gz |
[PATCH] m32r: Support M32104UT target platform
This patch is for supporting a new target platform, Renesas M32104UT
evaluation board.
The M32104UT is an eval board based on an uT-Engine specification. This board
has an MMU-less M32R family processor, M32104.
http://www-wa0.personal-media.co.jp/pmc/archive/te/te_m32104_e.pdf
This board is one of the most popular M32R platform, so we have ported
Linux/M32R to it.
Signed-off-by: Naoto Sugai <Sugai.Naoto@ak.MitsubishiElectric.co.jp>
Signed-off-by: Hirokazu Takata <takata@linux-m32r.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch/m32r/kernel/time.c')
-rw-r--r-- | arch/m32r/kernel/time.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/m32r/kernel/time.c b/arch/m32r/kernel/time.c index 2ebce20..b8e68b5 100644 --- a/arch/m32r/kernel/time.c +++ b/arch/m32r/kernel/time.c @@ -57,7 +57,7 @@ static unsigned long do_gettimeoffset(void) #if defined(CONFIG_CHIP_M32102) || defined(CONFIG_CHIP_XNUX2) \ || defined(CONFIG_CHIP_VDEC2) || defined(CONFIG_CHIP_M32700) \ - || defined(CONFIG_CHIP_OPSP) + || defined(CONFIG_CHIP_OPSP) || defined(CONFIG_CHIP_M32104) #ifndef CONFIG_SMP unsigned long count; @@ -268,7 +268,7 @@ void __init time_init(void) #if defined(CONFIG_CHIP_M32102) || defined(CONFIG_CHIP_XNUX2) \ || defined(CONFIG_CHIP_VDEC2) || defined(CONFIG_CHIP_M32700) \ - || defined(CONFIG_CHIP_OPSP) + || defined(CONFIG_CHIP_OPSP) || defined(CONFIG_CHIP_M32104) /* M32102 MFT setup */ setup_irq(M32R_IRQ_MFT2, &irq0); |