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author | Tejun Heo <tj@kernel.org> | 2009-10-02 13:28:56 +0900 |
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committer | Tejun Heo <tj@kernel.org> | 2009-10-02 13:28:56 +0900 |
commit | 52594762a39dfb6338c9d0906ca21dd9ae9453be (patch) | |
tree | 4c80dd59ec452c9fe798edf3f4023914c1898a0b /arch/ia64/kernel | |
parent | 36886478f59ec0fdc24a8877c572b92f8d416aba (diff) | |
download | op-kernel-dev-52594762a39dfb6338c9d0906ca21dd9ae9453be.zip op-kernel-dev-52594762a39dfb6338c9d0906ca21dd9ae9453be.tar.gz |
ia64: convert to dynamic percpu allocator
Unlike other archs, ia64 reserves space for percpu areas during early
memory initialization. These areas occupy a contiguous region indexed
by cpu number on contiguous memory model or are grouped by node on
discontiguous memory model.
As allocation and initialization are done by the arch code, all that
setup_per_cpu_areas() needs to do is communicating the determined
layout to the percpu allocator. This patch implements
setup_per_cpu_areas() for both contig and discontig memory models and
drops HAVE_LEGACY_PER_CPU_AREA.
Please note that for contig model, the allocation itself is modified
only to allocate for possible cpus instead of NR_CPUS. As dynamic
percpu allocator can handle non-direct mapping, there's no reason to
allocate memory for cpus which aren't possible.
Signed-off-by: Tejun Heo <tj@kernel.org>
Acked-by: Tony Luck <tony.luck@intel.com>
Cc: Fenghua Yu <fenghua.yu@intel.com>
Cc: linux-ia64 <linux-ia64@vger.kernel.org>
Diffstat (limited to 'arch/ia64/kernel')
-rw-r--r-- | arch/ia64/kernel/setup.c | 12 |
1 files changed, 0 insertions, 12 deletions
diff --git a/arch/ia64/kernel/setup.c b/arch/ia64/kernel/setup.c index 5d77c1e..bc1ef4a 100644 --- a/arch/ia64/kernel/setup.c +++ b/arch/ia64/kernel/setup.c @@ -855,18 +855,6 @@ identify_cpu (struct cpuinfo_ia64 *c) } /* - * In UP configuration, setup_per_cpu_areas() is defined in - * include/linux/percpu.h - */ -#ifdef CONFIG_SMP -void __init -setup_per_cpu_areas (void) -{ - /* start_kernel() requires this... */ -} -#endif - -/* * Do the following calculations: * * 1. the max. cache line size. |