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author | Vaibhav Hiremath <hvaibhav@ti.com> | 2012-06-18 00:47:27 -0600 |
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committer | Paul Walmsley <paul@pwsan.com> | 2012-06-18 12:08:06 -0600 |
commit | 3f0ea7645ae6d7111ebc3e83f47fbc0f2c8a8964 (patch) | |
tree | 6f000b859092336bcc27812e4b7022e200845817 /arch/h8300/README | |
parent | f969a6dcec75fe997a156b904d4fbbb5b313e54f (diff) | |
download | op-kernel-dev-3f0ea7645ae6d7111ebc3e83f47fbc0f2c8a8964.zip op-kernel-dev-3f0ea7645ae6d7111ebc3e83f47fbc0f2c8a8964.tar.gz |
ARM: OMAP AM33xx: powerdomains: add AM335x support
Add offset & mask fields to struct powerdomain
In case of AM33xx family of devices, there is no consistency between
PWRSTCTRL & PWRSTST register offsers in PRM space, for example -
PRM_XXX PWRSTCTRL PWRSTST
=======================================
PRM_PER_MOD: 0x0C, 0x08
PRM_WKUP_MOD: 0x04, 0x08
PRM_MPU_MOD: 0x00, 0x04
PRM_DEVICE_MOD: NA, NA
And also, there is no consistency between bit-offsets inside
PWRSTCTRL & PWRSTST register, for example -
PRM_XXX LOGICRET MEMON MEMRET
=======================================
GFX_PWRCTRL: 2, 17, 6
PER_PWRCTRL: 3, 25, 29
MPU_PWRCTRL: 2, 18, 22
WKUP_PWRCTRL: 3, NA, NA
This means, we need to maintain and pass on all this information
in powerdomain handle; so adding fields for,
- PWRSTCTRL/ST register offset
- Logic retention state mask
- mem_on/ret/pwrst/retst mask
Currently, this fields is only applicable and used for AM33XX devices.
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Kevin Hilman <khilman@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Rajendra Nayak <rnayak@ti.com>
[paul@pwsan.com: this patch is a combination of "Add offset & mask fields to
struct powerdomain" and the powerdomain portions of "ARM: OMAP3+: am33xx:
Add powerdomain & PRM support"; updated for 3.5]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/h8300/README')
0 files changed, 0 insertions, 0 deletions