summaryrefslogtreecommitdiffstats
path: root/arch/cris/include/asm
diff options
context:
space:
mode:
authorLinus Torvalds <torvalds@linux-foundation.org>2010-08-08 10:08:26 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2010-08-08 10:08:26 -0700
commit53bcef60633086ad73683d01a4ef9ca678484d2d (patch)
tree8b14cc031124d0aa0da6cd3b60115bc7eaa80061 /arch/cris/include/asm
parent4fd6c6bf83cb16321e9902b00e2af79054f4e0d6 (diff)
parent85d9865721c62a551547984e6cc8bd3ba732e294 (diff)
downloadop-kernel-dev-53bcef60633086ad73683d01a4ef9ca678484d2d.zip
op-kernel-dev-53bcef60633086ad73683d01a4ef9ca678484d2d.tar.gz
Merge branch 'for-linus' of git://www.jni.nu/cris
* 'for-linus' of git://www.jni.nu/cris: (51 commits) CRIS: Fix alignment problem for older ld CRIS: Always dump registers for segfaulting process. CRIS: Add config for pausing a seg-faulting process CRIS: Don't take faults while in_atomic CRIS: Fixup lookup for delay slot faults CRIS: Discard exit.text and .data at runtime CRIS: Add cache aligned and read mostly data sections CRIS: Return something from profile write CRIS: Add ARTPEC-3 and timestamps for sync-serial CRIS: Better ARTPEC-3 support for gpio CRIS: Add include guard CRIS: Better handling of pinmux settings CRIS: New DMA defines for ARTPEC-3 CRIS: __do_strncpy_from_user: Don't read the byte beyond the nil CRIS: Pagetable for ARTPEC-3 CRIS: Machine dependent memmap.h CRIS: Check if pointer is set before using it CRIS: Machine dependent dma.h CRIS: Define __read_mostly for CRISv32 CRIS: Discard .note.gnu.build-id section ...
Diffstat (limited to 'arch/cris/include/asm')
-rw-r--r--arch/cris/include/asm/etraxgpio.h96
-rw-r--r--arch/cris/include/asm/sync_serial.h27
2 files changed, 104 insertions, 19 deletions
diff --git a/arch/cris/include/asm/etraxgpio.h b/arch/cris/include/asm/etraxgpio.h
index 38f1c8e..d474818 100644
--- a/arch/cris/include/asm/etraxgpio.h
+++ b/arch/cris/include/asm/etraxgpio.h
@@ -21,31 +21,35 @@
* /dev/leds minor 2, Access to leds depending on kernelconfig
*
* For ARTPEC-3 (CONFIG_CRIS_MACH_ARTPEC3):
- * /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction
- * /dev/gpiob minor 1, 18 bit GPIO, each bit can change direction
- * /dev/gpioc minor 3, 18 bit GPIO, each bit can change direction
- * /dev/gpiod minor 4, 18 bit GPIO, each bit can change direction
+ * /dev/gpioa minor 0, 32 bit GPIO, each bit can change direction
+ * /dev/gpiob minor 1, 32 bit GPIO, each bit can change direction
+ * /dev/gpioc minor 3, 16 bit GPIO, each bit can change direction
+ * /dev/gpiod minor 4, 32 bit GPIO, input only
* /dev/leds minor 2, Access to leds depending on kernelconfig
* /dev/pwm0 minor 16, PWM channel 0 on PA30
* /dev/pwm1 minor 17, PWM channel 1 on PA31
* /dev/pwm2 minor 18, PWM channel 2 on PB26
+ * /dev/ppwm minor 19, PPWM channel
*
*/
#ifndef _ASM_ETRAXGPIO_H
#define _ASM_ETRAXGPIO_H
+#define GPIO_MINOR_FIRST 0
+
+#define ETRAXGPIO_IOCTYPE 43
+
/* etraxgpio _IOC_TYPE, bits 8 to 15 in ioctl cmd */
#ifdef CONFIG_ETRAX_ARCH_V10
-#define ETRAXGPIO_IOCTYPE 43
#define GPIO_MINOR_A 0
#define GPIO_MINOR_B 1
#define GPIO_MINOR_LEDS 2
#define GPIO_MINOR_G 3
#define GPIO_MINOR_LAST 3
+#define GPIO_MINOR_LAST_REAL GPIO_MINOR_LAST
#endif
#ifdef CONFIG_ETRAXFS
-#define ETRAXGPIO_IOCTYPE 43
#define GPIO_MINOR_A 0
#define GPIO_MINOR_B 1
#define GPIO_MINOR_LEDS 2
@@ -58,10 +62,10 @@
#else
#define GPIO_MINOR_LAST 5
#endif
+#define GPIO_MINOR_LAST_REAL GPIO_MINOR_LAST
#endif
#ifdef CONFIG_CRIS_MACH_ARTPEC3
-#define ETRAXGPIO_IOCTYPE 43
#define GPIO_MINOR_A 0
#define GPIO_MINOR_B 1
#define GPIO_MINOR_LEDS 2
@@ -73,12 +77,17 @@
#else
#define GPIO_MINOR_LAST 4
#endif
-#define GPIO_MINOR_PWM0 16
-#define GPIO_MINOR_PWM1 17
-#define GPIO_MINOR_PWM2 18
-#define GPIO_MINOR_LAST_PWM GPIO_MINOR_PWM2
+#define GPIO_MINOR_FIRST_PWM 16
+#define GPIO_MINOR_PWM0 (GPIO_MINOR_FIRST_PWM+0)
+#define GPIO_MINOR_PWM1 (GPIO_MINOR_FIRST_PWM+1)
+#define GPIO_MINOR_PWM2 (GPIO_MINOR_FIRST_PWM+2)
+#define GPIO_MINOR_PPWM (GPIO_MINOR_FIRST_PWM+3)
+#define GPIO_MINOR_LAST_PWM GPIO_MINOR_PPWM
+#define GPIO_MINOR_LAST_REAL GPIO_MINOR_LAST_PWM
#endif
+
+
/* supported ioctl _IOC_NR's */
#define IO_READBITS 0x1 /* read and return current port bits (obsolete) */
@@ -125,12 +134,10 @@
*/
#define IO_READ_INBITS 0x10 /* *arg is result of reading the input pins */
#define IO_READ_OUTBITS 0x11 /* *arg is result of reading the output shadow */
-#define IO_SETGET_INPUT 0x12 /* bits set in *arg is set to input,
- * *arg updated with current input pins.
- */
-#define IO_SETGET_OUTPUT 0x13 /* bits set in *arg is set to output,
- * *arg updated with current output pins.
- */
+#define IO_SETGET_INPUT 0x12 /* bits set in *arg is set to input, */
+ /* *arg updated with current input pins. */
+#define IO_SETGET_OUTPUT 0x13 /* bits set in *arg is set to output, */
+ /* *arg updated with current output pins. */
/* The following ioctl's are applicable to the PWM channels only */
@@ -140,7 +147,8 @@ enum io_pwm_mode {
PWM_OFF = 0, /* disabled, deallocated */
PWM_STANDARD = 1, /* 390 kHz, duty cycle 0..255/256 */
PWM_FAST = 2, /* variable freq, w/ 10ns active pulse len */
- PWM_VARFREQ = 3 /* individually configurable high/low periods */
+ PWM_VARFREQ = 3, /* individually configurable high/low periods */
+ PWM_SOFT = 4 /* software generated */
};
struct io_pwm_set_mode {
@@ -176,4 +184,56 @@ struct io_pwm_set_duty {
int duty; /* 0..255 */
};
+/* Returns information about the latest PWM pulse.
+ * lo: Length of the latest low period, in units of 10ns.
+ * hi: Length of the latest high period, in units of 10ns.
+ * cnt: Time since last detected edge, in units of 10ns.
+ *
+ * The input source to PWM is decied by IO_PWM_SET_INPUT_SRC.
+ *
+ * NOTE: All PWM devices is connected to the same input source.
+ */
+#define IO_PWM_GET_PERIOD 0x23
+
+struct io_pwm_get_period {
+ unsigned int lo;
+ unsigned int hi;
+ unsigned int cnt;
+};
+
+/* Sets the input source for the PWM input. For the src value see the
+ * register description for gio:rw_pwm_in_cfg.
+ *
+ * NOTE: All PWM devices is connected to the same input source.
+ */
+#define IO_PWM_SET_INPUT_SRC 0x24
+struct io_pwm_set_input_src {
+ unsigned int src; /* 0..7 */
+};
+
+/* Sets the duty cycles in steps of 1/256, 0 = 0%, 255 = 100% duty cycle */
+#define IO_PPWM_SET_DUTY 0x25
+
+struct io_ppwm_set_duty {
+ int duty; /* 0..255 */
+};
+
+/* Configuraton struct for the IO_PWMCLK_SET_CONFIG ioctl to configure
+ * PWM capable gpio pins:
+ */
+#define IO_PWMCLK_SETGET_CONFIG 0x26
+struct gpio_pwmclk_conf {
+ unsigned int gpiopin; /* The pin number based on the opened device */
+ unsigned int baseclk; /* The base clock to use, or sw will select one close*/
+ unsigned int low; /* The number of low periods of the baseclk */
+ unsigned int high; /* The number of high periods of the baseclk */
+};
+
+/* Examples:
+ * To get a symmetric 12 MHz clock without knowing anything about the hardware:
+ * baseclk = 12000000, low = 0, high = 0
+ * To just get info of current setting:
+ * baseclk = 0, low = 0, high = 0, the values will be updated by driver.
+ */
+
#endif
diff --git a/arch/cris/include/asm/sync_serial.h b/arch/cris/include/asm/sync_serial.h
index d87c24d..7f827fe 100644
--- a/arch/cris/include/asm/sync_serial.h
+++ b/arch/cris/include/asm/sync_serial.h
@@ -19,6 +19,7 @@
#define SSP_OPOLARITY _IOR('S', 4, unsigned int)
#define SSP_SPI _IOR('S', 5, unsigned int)
#define SSP_INBUFCHUNK _IOR('S', 6, unsigned int)
+#define SSP_INPUT _IOR('S', 7, unsigned int)
/* Values for SSP_SPEED */
#define SSP150 0
@@ -37,6 +38,7 @@
#define SSP921600 13
#define SSP3125000 14
#define CODEC 15
+#define CODEC_f32768 16
#define FREQ_4MHz 0
#define FREQ_2MHz 1
@@ -46,9 +48,14 @@
#define FREQ_128kHz 5
#define FREQ_64kHz 6
#define FREQ_32kHz 7
+/* FREQ_* with values where bit (value & 0x10) is set are */
+/* used for CODEC_f32768 */
+#define FREQ_4096kHz 16 /* CODEC_f32768 */
/* Used by application to set CODEC divider, word rate and frame rate */
-#define CODEC_VAL(freq, clk_per_sync, sync_per_frame) (CODEC | (freq << 8) | (clk_per_sync << 16) | (sync_per_frame << 28))
+#define CODEC_VAL(freq, clk_per_sync, sync_per_frame) \
+ ((CODEC + ((freq & 0x10) >> 4)) | (freq << 8) | \
+ (clk_per_sync << 16) | (sync_per_frame << 28))
/* Used by driver to extract speed */
#define GET_SPEED(x) (x & 0xff)
@@ -68,6 +75,7 @@
#define NORMAL_SYNC 1
#define EARLY_SYNC 2
#define SECOND_WORD_SYNC 0x40000
+#define LATE_SYNC 0x80000
#define BIT_SYNC 4
#define WORD_SYNC 8
@@ -104,4 +112,21 @@
/* Values for SSP_INBUFCHUNK */
/* plain integer with the size of DMA chunks */
+/* To ensure that the timestamps are aligned with the data being read
+ * the read length MUST be a multiple of the length of the DMA buffers.
+ *
+ * Use a multiple of SSP_INPUT_CHUNK_SIZE defined below.
+ */
+#define SSP_INPUT_CHUNK_SIZE 256
+
+/* Request struct to pass through the ioctl interface to read
+ * data with timestamps.
+ */
+struct ssp_request {
+ char __user *buf; /* Where to put the data. */
+ size_t len; /* Size of buf. MUST be a multiple of */
+ /* SSP_INPUT_CHUNK_SIZE! */
+ struct timespec ts; /* The time the data was sampled. */
+};
+
#endif
OpenPOWER on IntegriCloud