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author | David S. Miller <davem@davemloft.net> | 2010-08-16 14:09:34 -0700 |
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committer | David S. Miller <davem@davemloft.net> | 2010-08-16 14:09:34 -0700 |
commit | 300a103d1504134f8c4a7e831f995e917ea9b1e4 (patch) | |
tree | 7f94d5fff513d132bd0b57a9e3bd96c4cc80d707 /arch/cris/arch-v32/mach-a3/dram_init.S | |
parent | 0a492896ac07336c98f37ad7fab4a6387b6ada78 (diff) | |
parent | da5cabf80e2433131bf0ed8993abc0f7ea618c73 (diff) | |
download | op-kernel-dev-300a103d1504134f8c4a7e831f995e917ea9b1e4.zip op-kernel-dev-300a103d1504134f8c4a7e831f995e917ea9b1e4.tar.gz |
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
Diffstat (limited to 'arch/cris/arch-v32/mach-a3/dram_init.S')
-rw-r--r-- | arch/cris/arch-v32/mach-a3/dram_init.S | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/arch/cris/arch-v32/mach-a3/dram_init.S b/arch/cris/arch-v32/mach-a3/dram_init.S index 94d6b41..ec8648b 100644 --- a/arch/cris/arch-v32/mach-a3/dram_init.S +++ b/arch/cris/arch-v32/mach-a3/dram_init.S @@ -24,11 +24,21 @@ ;; Refer to ddr2 MDS for initialization sequence + ; 2. Wait 200us + move.d 10000, $r2 +1: bne 1b + subq 1, $r2 + ; Start clock move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_phy_cfg), $r0 move.d REG_STATE(ddr2, rw_phy_cfg, en, yes), $r1 move.d $r1, [$r0] + ; 2. Wait 200us + move.d 10000, $r2 +1: bne 1b + subq 1, $r2 + ; Reset phy and start calibration move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_phy_ctrl), $r0 move.d REG_STATE(ddr2, rw_phy_ctrl, rst, yes) | \ @@ -52,6 +62,10 @@ do_cmd: lslq 16, $r1 or.d $r3, $r1 move.d $r1, [$r0] + ; 2. Wait 200us + move.d 10000, $r4 +1: bne 1b + subq 1, $r4 cmp.d sdram_commands_end, $r2 blo command_loop nop @@ -63,7 +77,7 @@ do_cmd: ; Set latency move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_latency), $r0 - move.d 0x13, $r1 + move.d CONFIG_ETRAX_DDR2_LATENCY, $r1 move.d $r1, [$r0] ; Set configuration |