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authorMike Frysinger <vapier@gentoo.org>2011-05-02 00:00:35 -0400
committerMike Frysinger <vapier@gentoo.org>2011-05-25 08:13:43 -0400
commit803103925b1f23fe0edf91348be3e5a8fd352d5e (patch)
tree40b84f804c9ba8178b60b3e742cd2a4d193b2be6 /arch/blackfin
parentf91c69168a218fb7ab7a5ce09fa1ccd20a904119 (diff)
downloadop-kernel-dev-803103925b1f23fe0edf91348be3e5a8fd352d5e.zip
op-kernel-dev-803103925b1f23fe0edf91348be3e5a8fd352d5e.tar.gz
Blackfin: use on-chip reset func with newer parts
Turns out the documentation is wrong and doing "RAISE 1" does not result in a software reset, only a core reset. So when the on-chip rom has a functioning reset helper, use it. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin')
-rw-r--r--arch/blackfin/kernel/reboot.c65
1 files changed, 31 insertions, 34 deletions
diff --git a/arch/blackfin/kernel/reboot.c b/arch/blackfin/kernel/reboot.c
index 53d08de..488bdc5 100644
--- a/arch/blackfin/kernel/reboot.c
+++ b/arch/blackfin/kernel/reboot.c
@@ -23,6 +23,9 @@
__attribute__ ((__l1_text__, __noreturn__))
static void bfin_reset(void)
{
+ if (!ANOMALY_05000353 && !ANOMALY_05000386)
+ bfrom_SoftReset((void *)(L1_SCRATCH_START + L1_SCRATCH_LENGTH - 20));
+
/* Wait for completion of "system" events such as cache line
* line fills so that we avoid infinite stalls later on as
* much as possible. This code is in L1, so it won't trigger
@@ -30,46 +33,40 @@ static void bfin_reset(void)
*/
__builtin_bfin_ssync();
- /* The bootrom checks to see how it was reset and will
- * automatically perform a software reset for us when
- * it starts executing after the core reset.
- */
- if (ANOMALY_05000353 || ANOMALY_05000386) {
- /* Initiate System software reset. */
- bfin_write_SWRST(0x7);
+ /* Initiate System software reset. */
+ bfin_write_SWRST(0x7);
- /* Due to the way reset is handled in the hardware, we need
- * to delay for 10 SCLKS. The only reliable way to do this is
- * to calculate the CCLK/SCLK ratio and multiply 10. For now,
- * we'll assume worse case which is a 1:15 ratio.
- */
- asm(
- "LSETUP (1f, 1f) LC0 = %0\n"
- "1: nop;"
- :
- : "a" (15 * 10)
- : "LC0", "LB0", "LT0"
- );
+ /* Due to the way reset is handled in the hardware, we need
+ * to delay for 10 SCLKS. The only reliable way to do this is
+ * to calculate the CCLK/SCLK ratio and multiply 10. For now,
+ * we'll assume worse case which is a 1:15 ratio.
+ */
+ asm(
+ "LSETUP (1f, 1f) LC0 = %0\n"
+ "1: nop;"
+ :
+ : "a" (15 * 10)
+ : "LC0", "LB0", "LT0"
+ );
- /* Clear System software reset */
- bfin_write_SWRST(0);
+ /* Clear System software reset */
+ bfin_write_SWRST(0);
- /* The BF526 ROM will crash during reset */
+ /* The BF526 ROM will crash during reset */
#if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
- bfin_read_SWRST();
+ bfin_read_SWRST();
#endif
- /* Wait for the SWRST write to complete. Cannot rely on SSYNC
- * though as the System state is all reset now.
- */
- asm(
- "LSETUP (1f, 1f) LC1 = %0\n"
- "1: nop;"
- :
- : "a" (15 * 1)
- : "LC1", "LB1", "LT1"
- );
- }
+ /* Wait for the SWRST write to complete. Cannot rely on SSYNC
+ * though as the System state is all reset now.
+ */
+ asm(
+ "LSETUP (1f, 1f) LC1 = %0\n"
+ "1: nop;"
+ :
+ : "a" (15 * 1)
+ : "LC1", "LB1", "LT1"
+ );
while (1)
/* Issue core reset */
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