diff options
| author | Dmitry Torokhov <dmitry.torokhov@gmail.com> | 2013-11-14 17:38:05 -0800 |
|---|---|---|
| committer | Dmitry Torokhov <dmitry.torokhov@gmail.com> | 2013-11-14 17:38:05 -0800 |
| commit | 42249094f79422fbf5ed4b54eeb48ff096809b8f (patch) | |
| tree | 91e6850c8c7e8cc284cf8bb6363f8662f84011f4 /arch/blackfin | |
| parent | 936816161978ca716a56c5e553c68f25972b1e3a (diff) | |
| parent | 2c027b7c48a888ab173ba45babb4525e278375d9 (diff) | |
| download | op-kernel-dev-42249094f79422fbf5ed4b54eeb48ff096809b8f.zip op-kernel-dev-42249094f79422fbf5ed4b54eeb48ff096809b8f.tar.gz | |
Merge branch 'next' into for-linus
Merge first round of changes for 3.13 merge window.
Diffstat (limited to 'arch/blackfin')
29 files changed, 2280 insertions, 247 deletions
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index a117652..f78c9a2 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig @@ -32,7 +32,6 @@ config BLACKFIN select HAVE_UNDERSCORE_SYMBOL_PREFIX select VIRT_TO_BUS select ARCH_WANT_IPC_PARSE_VERSION - select HAVE_GENERIC_HARDIRQS select GENERIC_ATOMIC64 select GENERIC_IRQ_PROBE select USE_GENERIC_SMP_HELPERS if SMP @@ -41,6 +40,7 @@ config BLACKFIN select ARCH_USES_GETTIMEOFFSET if !GENERIC_CLOCKEVENTS select HAVE_MOD_ARCH_SPECIFIC select MODULES_USE_ELF_RELA + select HAVE_DEBUG_STACKOVERFLOW config GENERIC_CSUM def_bool y @@ -253,7 +253,7 @@ config NR_CPUS config HOTPLUG_CPU bool "Support for hot-pluggable CPUs" - depends on SMP && HOTPLUG + depends on SMP default y config BF_REV_MIN @@ -282,7 +282,7 @@ config BF_REV_0_0 config BF_REV_0_1 bool "0.1" - depends on (BF51x || BF52x || (BF54x && !BF54xM)) + depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x) config BF_REV_0_2 bool "0.2" diff --git a/arch/blackfin/Kconfig.debug b/arch/blackfin/Kconfig.debug index 79594694..f3337ee 100644 --- a/arch/blackfin/Kconfig.debug +++ b/arch/blackfin/Kconfig.debug @@ -2,13 +2,6 @@ menu "Kernel hacking" source "lib/Kconfig.debug" -config DEBUG_STACKOVERFLOW - bool "Check for stack overflows" - depends on DEBUG_KERNEL - help - This option will cause messages to be printed if free stack space - drops below a certain limit. - config DEBUG_VERBOSE bool "Verbose fault messages" default y diff --git a/arch/blackfin/boot/.gitignore b/arch/blackfin/boot/.gitignore index 229e508..1287a54 100644 --- a/arch/blackfin/boot/.gitignore +++ b/arch/blackfin/boot/.gitignore @@ -1,2 +1,3 @@ vmImage* vmlinux* +uImage* diff --git a/arch/blackfin/include/asm/bfin6xx_spi.h b/arch/blackfin/include/asm/bfin_spi3.h index 89370b6..0957e65a 100644 --- a/arch/blackfin/include/asm/bfin6xx_spi.h +++ b/arch/blackfin/include/asm/bfin_spi3.h @@ -240,7 +240,7 @@ struct bfin_spi_regs { #define MAX_CTRL_CS 8 /* cs in spi controller */ /* device.platform_data for SSP controller devices */ -struct bfin6xx_spi_master { +struct bfin_spi3_master { u16 num_chipselect; u16 pin_req[7]; }; @@ -248,7 +248,7 @@ struct bfin6xx_spi_master { /* spi_board_info.controller_data for SPI slave devices, * copied to spi_device.platform_data ... mostly for dma tuning */ -struct bfin6xx_spi_chip { +struct bfin_spi3_chip { u32 control; u16 cs_chg_udelay; /* Some devices require 16-bit delays */ u32 tx_dummy_val; /* tx value for rx only transfer */ diff --git a/arch/blackfin/include/asm/pgtable.h b/arch/blackfin/include/asm/pgtable.h index b866392..0b04901 100644 --- a/arch/blackfin/include/asm/pgtable.h +++ b/arch/blackfin/include/asm/pgtable.h @@ -88,7 +88,6 @@ extern char empty_zero_page[]; * No page table caches to initialise. */ #define pgtable_cache_init() do { } while (0) -#define io_remap_pfn_range remap_pfn_range /* * All 32bit addresses are effectively valid for vmalloc... diff --git a/arch/blackfin/include/asm/scb.h b/arch/blackfin/include/asm/scb.h new file mode 100644 index 0000000..a294cc0 --- /dev/null +++ b/arch/blackfin/include/asm/scb.h @@ -0,0 +1,21 @@ +/* + * arch/blackfin/mach-common/scb-init.c - reprogram system cross bar priority + * + * Copyright 2012 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#define SCB_SLOT_OFFSET 24 +#define SCB_MI_MAX_SLOT 32 + +struct scb_mi_prio { + unsigned long scb_mi_arbr; + unsigned long scb_mi_arbw; + unsigned char scb_mi_slots; + unsigned char scb_mi_prio[SCB_MI_MAX_SLOT]; +}; + +extern struct scb_mi_prio scb_data[]; + +extern void init_scb(void); diff --git a/arch/blackfin/kernel/kgdb.c b/arch/blackfin/kernel/kgdb.c index b882ce2..fa53fae 100644 --- a/arch/blackfin/kernel/kgdb.c +++ b/arch/blackfin/kernel/kgdb.c @@ -9,6 +9,7 @@ #include <linux/ptrace.h> /* for linux pt_regs struct */ #include <linux/kgdb.h> #include <linux/uaccess.h> +#include <asm/irq_regs.h> void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs) { diff --git a/arch/blackfin/kernel/perf_event.c b/arch/blackfin/kernel/perf_event.c index e47d19a..974e554 100644 --- a/arch/blackfin/kernel/perf_event.c +++ b/arch/blackfin/kernel/perf_event.c @@ -468,7 +468,7 @@ static void bfin_pmu_setup(int cpu) memset(cpuhw, 0, sizeof(struct cpu_hw_events)); } -static int __cpuinit +static int bfin_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu) { unsigned int cpu = (long)hcpu; diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c index 107b306..3961930 100644 --- a/arch/blackfin/kernel/setup.c +++ b/arch/blackfin/kernel/setup.c @@ -35,6 +35,9 @@ #ifdef CONFIG_BF60x #include <mach/pm.h> #endif +#ifdef CONFIG_SCB_PRIORITY +#include <asm/scb.h> +#endif u16 _bfin_swrst; EXPORT_SYMBOL(_bfin_swrst); @@ -99,7 +102,7 @@ void __init generate_cplb_tables(void) } #endif -void __cpuinit bfin_setup_caches(unsigned int cpu) +void bfin_setup_caches(unsigned int cpu) { #ifdef CONFIG_BFIN_ICACHE bfin_icache_init(icplb_tbl[cpu]); @@ -165,7 +168,7 @@ void __cpuinit bfin_setup_caches(unsigned int cpu) #endif } -void __cpuinit bfin_setup_cpudata(unsigned int cpu) +void bfin_setup_cpudata(unsigned int cpu) { struct blackfin_cpudata *cpudata = &per_cpu(cpu_data, cpu); @@ -1101,6 +1104,9 @@ void __init setup_arch(char **cmdline_p) #endif init_exception_vectors(); bfin_cache_init(); /* Initialize caches for the boot CPU */ +#ifdef CONFIG_SCB_PRIORITY + init_scb(); +#endif } static int __init topology_init(void) diff --git a/arch/blackfin/mach-bf527/boards/ad7160eval.c b/arch/blackfin/mach-bf527/boards/ad7160eval.c index d58f50e..1e7be62 100644 --- a/arch/blackfin/mach-bf527/boards/ad7160eval.c +++ b/arch/blackfin/mach-bf527/boards/ad7160eval.c @@ -283,14 +283,6 @@ static struct platform_device bfin_i2s = { }; #endif -#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) -static struct platform_device bfin_tdm = { - .name = "bfin-tdm", - .id = CONFIG_SND_BF5XX_SPORT_NUM, - /* TODO: add platform data here */ -}; -#endif - static struct spi_board_info bfin_spi_board_info[] __initdata = { #if defined(CONFIG_MTD_M25P80) \ || defined(CONFIG_MTD_M25P80_MODULE) @@ -800,10 +792,6 @@ static struct platform_device *stamp_devices[] __initdata = { #if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) &bfin_i2s, #endif - -#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) - &bfin_tdm, -#endif }; static int __init ad7160eval_init(void) diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c index 29f16e5..d0a0c5e 100644 --- a/arch/blackfin/mach-bf527/boards/ezkit.c +++ b/arch/blackfin/mach-bf527/boards/ezkit.c @@ -493,8 +493,7 @@ static const struct ad7879_platform_data bfin_ad7879_ts_info = { }; #endif -#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \ - defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) +#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) static const u16 bfin_snd_pin[][7] = { {P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, @@ -549,13 +548,6 @@ static struct platform_device bfin_i2s_pcm = { }; #endif -#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) -static struct platform_device bfin_tdm_pcm = { - .name = "bfin-tdm-pcm-audio", - .id = -1, -}; -#endif - #if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE) static struct platform_device bfin_ac97_pcm = { .name = "bfin-ac97-pcm-audio", @@ -575,22 +567,10 @@ static struct platform_device bfin_i2s = { }; #endif -#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) -static struct platform_device bfin_tdm = { - .name = "bfin-tdm", - .id = CONFIG_SND_BF5XX_SPORT_NUM, - .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]), - .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM], - .dev = { - .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM], - }, -}; -#endif - #if defined(CONFIG_SND_BF5XX_SOC_AD1836) \ || defined(CONFIG_SND_BF5XX_SOC_AD1836_MODULE) static const char * const ad1836_link[] = { - "bfin-tdm.0", + "bfin-i2s.0", "spi0.4", }; static struct platform_device bfin_ad1836_machine = { @@ -1269,10 +1249,6 @@ static struct platform_device *stamp_devices[] __initdata = { &bfin_i2s_pcm, #endif -#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) - &bfin_tdm_pcm, -#endif - #if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE) &bfin_ac97_pcm, #endif @@ -1281,10 +1257,6 @@ static struct platform_device *stamp_devices[] __initdata = { &bfin_i2s, #endif -#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) - &bfin_tdm, -#endif - #if defined(CONFIG_SND_BF5XX_SOC_AD1836) || \ defined(CONFIG_SND_BF5XX_SOC_AD1836_MODULE) &bfin_ad1836_machine, diff --git a/arch/blackfin/mach-bf533/boards/ezkit.c b/arch/blackfin/mach-bf533/boards/ezkit.c index 07811c2..90fb0d1 100644 --- a/arch/blackfin/mach-bf533/boards/ezkit.c +++ b/arch/blackfin/mach-bf533/boards/ezkit.c @@ -450,14 +450,6 @@ static struct platform_device bfin_i2s = { }; #endif -#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) -static struct platform_device bfin_tdm = { - .name = "bfin-tdm", - .id = CONFIG_SND_BF5XX_SPORT_NUM, - /* TODO: add platform data here */ -}; -#endif - #if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE) static struct platform_device bfin_ac97 = { .name = "bfin-ac97", @@ -516,10 +508,6 @@ static struct platform_device *ezkit_devices[] __initdata = { &bfin_i2s, #endif -#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) - &bfin_tdm, -#endif - #if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE) &bfin_ac97, #endif diff --git a/arch/blackfin/mach-bf533/boards/stamp.c b/arch/blackfin/mach-bf533/boards/stamp.c index 6fca869..4a8c2e3 100644 --- a/arch/blackfin/mach-bf533/boards/stamp.c +++ b/arch/blackfin/mach-bf533/boards/stamp.c @@ -542,8 +542,7 @@ static struct platform_device bfin_dpmc = { }; #if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \ - defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) \ - || defined(CONFIG_SND_BF5XX_AC97) || \ + defined(CONFIG_SND_BF5XX_AC97) || \ defined(CONFIG_SND_BF5XX_AC97_MODULE) #include <asm/bfin_sport.h> @@ -603,13 +602,6 @@ static struct platform_device bfin_i2s_pcm = { }; #endif -#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) -static struct platform_device bfin_tdm_pcm = { - .name = "bfin-tdm-pcm-audio", - .id = -1, -}; -#endif - #if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE) static struct platform_device bfin_ac97_pcm = { .name = "bfin-ac97-pcm-audio", @@ -620,7 +612,7 @@ static struct platform_device bfin_ac97_pcm = { #if defined(CONFIG_SND_BF5XX_SOC_AD1836) \ || defined(CONFIG_SND_BF5XX_SOC_AD1836_MODULE) static const char * const ad1836_link[] = { - "bfin-tdm.0", + "bfin-i2s.0", "spi0.4", }; static struct platform_device bfin_ad1836_machine = { @@ -675,20 +667,6 @@ static struct platform_device bfin_i2s = { }; #endif -#if defined(CONFIG_SND_BF5XX_SOC_TDM) || \ - defined(CONFIG_SND_BF5XX_SOC_TDM_MODULE) -static struct platform_device bfin_tdm = { - .name = "bfin-tdm", - .id = CONFIG_SND_BF5XX_SPORT_NUM, - .num_resources = - ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]), - .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM], - .dev = { - .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM], - }, -}; -#endif - #if defined(CONFIG_SND_BF5XX_SOC_AC97) || \ defined(CONFIG_SND_BF5XX_SOC_AC97_MODULE) static struct platform_device bfin_ac97 = { @@ -761,10 +739,6 @@ static struct platform_device *stamp_devices[] __initdata = { &bfin_i2s_pcm, #endif -#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) - &bfin_tdm_pcm, -#endif - #if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE) &bfin_ac97_pcm, #endif @@ -792,11 +766,6 @@ static struct platform_device *stamp_devices[] __initdata = { &bfin_i2s, #endif -#if defined(CONFIG_SND_BF5XX_SOC_TDM) || \ - defined(CONFIG_SND_BF5XX_SOC_TDM_MODULE) - &bfin_tdm, -#endif - #if defined(CONFIG_SND_BF5XX_SOC_AC97) || \ defined(CONFIG_SND_BF5XX_SOC_AC97_MODULE) &bfin_ac97, diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c index 6a3a14b..44fd1d4 100644 --- a/arch/blackfin/mach-bf537/boards/stamp.c +++ b/arch/blackfin/mach-bf537/boards/stamp.c @@ -2570,7 +2570,6 @@ static struct platform_device bfin_dpmc = { }; #if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \ - defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) || \ defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE) #define SPORT_REQ(x) \ @@ -2628,13 +2627,6 @@ static struct platform_device bfin_i2s_pcm = { }; #endif -#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) -static struct platform_device bfin_tdm_pcm = { - .name = "bfin-tdm-pcm-audio", - .id = -1, -}; -#endif - #if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE) static struct platform_device bfin_ac97_pcm = { .name = "bfin-ac97-pcm-audio", @@ -2645,7 +2637,7 @@ static struct platform_device bfin_ac97_pcm = { #if defined(CONFIG_SND_BF5XX_SOC_AD1836) \ || defined(CONFIG_SND_BF5XX_SOC_AD1836_MODULE) static const char * const ad1836_link[] = { - "bfin-tdm.0", + "bfin-i2s.0", "spi0.4", }; static struct platform_device bfin_ad1836_machine = { @@ -2699,18 +2691,6 @@ static struct platform_device bfin_i2s = { }; #endif -#if defined(CONFIG_SND_BF5XX_SOC_TDM) || defined(CONFIG_SND_BF5XX_SOC_TDM_MODULE) -static struct platform_device bfin_tdm = { - .name = "bfin-tdm", - .id = CONFIG_SND_BF5XX_SPORT_NUM, - .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]), - .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM], - .dev = { - .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM], - }, -}; -#endif - #if defined(CONFIG_SND_BF5XX_SOC_AC97) || defined(CONFIG_SND_BF5XX_SOC_AC97_MODULE) static struct platform_device bfin_ac97 = { .name = "bfin-ac97", @@ -2935,10 +2915,6 @@ static struct platform_device *stamp_devices[] __initdata = { &bfin_i2s_pcm, #endif -#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) - &bfin_tdm_pcm, -#endif - #if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE) &bfin_ac97_pcm, #endif @@ -2961,10 +2937,6 @@ static struct platform_device *stamp_devices[] __initdata = { &bfin_i2s, #endif -#if defined(CONFIG_SND_BF5XX_SOC_TDM) || defined(CONFIG_SND_BF5XX_SOC_TDM_MODULE) - &bfin_tdm, -#endif - #if defined(CONFIG_SND_BF5XX_SOC_AC97) || defined(CONFIG_SND_BF5XX_SOC_AC97_MODULE) &bfin_ac97, #endif diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c index c4d07f0..372eb54 100644 --- a/arch/blackfin/mach-bf548/boards/ezkit.c +++ b/arch/blackfin/mach-bf548/boards/ezkit.c @@ -1393,7 +1393,6 @@ static struct platform_device bfin_dpmc = { }; #if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \ - defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) || \ defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE) #define SPORT_REQ(x) \ @@ -1461,13 +1460,6 @@ static struct platform_device bfin_i2s_pcm = { }; #endif -#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) -static struct platform_device bfin_tdm_pcm = { - .name = "bfin-tdm-pcm-audio", - .id = -1, -}; -#endif - #if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE) static struct platform_device bfin_ac97_pcm = { .name = "bfin-ac97-pcm-audio", @@ -1501,18 +1493,6 @@ static struct platform_device bfin_i2s = { }; #endif -#if defined(CONFIG_SND_BF5XX_SOC_TDM) || defined(CONFIG_SND_BF5XX_SOC_TDM_MODULE) -static struct platform_device bfin_tdm = { - .name = "bfin-tdm", - .id = CONFIG_SND_BF5XX_SPORT_NUM, - .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]), - .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM], - .dev = { - .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM], - }, -}; -#endif - #if defined(CONFIG_SND_BF5XX_SOC_AC97) || defined(CONFIG_SND_BF5XX_SOC_AC97_MODULE) static struct platform_device bfin_ac97 = { .name = "bfin-ac97", @@ -1646,9 +1626,7 @@ static struct platform_device *ezkit_devices[] __initdata = { #if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) &bfin_i2s_pcm, #endif -#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) - &bfin_tdm_pcm, -#endif + #if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE) &bfin_ac97_pcm, #endif @@ -1661,10 +1639,6 @@ static struct platform_device *ezkit_devices[] __initdata = { &bfin_i2s, #endif -#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) - &bfin_tdm, -#endif - #if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE) &bfin_ac97, #endif diff --git a/arch/blackfin/mach-bf561/boards/ezkit.c b/arch/blackfin/mach-bf561/boards/ezkit.c index 551f866..92938e7 100644 --- a/arch/blackfin/mach-bf561/boards/ezkit.c +++ b/arch/blackfin/mach-bf561/boards/ezkit.c @@ -523,14 +523,6 @@ static struct platform_device bfin_i2s = { }; #endif -#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) -static struct platform_device bfin_tdm = { - .name = "bfin-tdm", - .id = CONFIG_SND_BF5XX_SPORT_NUM, - /* TODO: add platform data here */ -}; -#endif - #if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE) static struct platform_device bfin_ac97 = { .name = "bfin-ac97", @@ -542,7 +534,7 @@ static struct platform_device bfin_ac97 = { #if defined(CONFIG_SND_BF5XX_SOC_AD1836) \ || defined(CONFIG_SND_BF5XX_SOC_AD1836_MODULE) static const char * const ad1836_link[] = { - "bfin-tdm.0", + "bfin-i2s.0", "spi0.4", }; static struct platform_device bfin_ad1836_machine = { @@ -611,10 +603,6 @@ static struct platform_device *ezkit_devices[] __initdata = { &bfin_i2s, #endif -#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) - &bfin_tdm, -#endif - #if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE) &bfin_ac97, #endif diff --git a/arch/blackfin/mach-bf561/smp.c b/arch/blackfin/mach-bf561/smp.c index ab1c617..11789be 100644 --- a/arch/blackfin/mach-bf561/smp.c +++ b/arch/blackfin/mach-bf561/smp.c @@ -48,7 +48,7 @@ int __init setup_profiling_timer(unsigned int multiplier) /* not supported */ return -EINVAL; } -void __cpuinit platform_secondary_init(unsigned int cpu) +void platform_secondary_init(unsigned int cpu) { /* Clone setup for peripheral interrupt sources from CoreA. */ bfin_write_SICB_IMASK0(bfin_read_SIC_IMASK0()); @@ -69,12 +69,11 @@ void __cpuinit platform_secondary_init(unsigned int cpu) SSYNC(); /* We are done with local CPU inits, unblock the boot CPU. */ - set_cpu_online(cpu, true); spin_lock(&boot_lock); spin_unlock(&boot_lock); } -int __cpuinit platform_boot_secondary(unsigned int cpu, struct task_struct *idle) +int platform_boot_secondary(unsigned int cpu, struct task_struct *idle) { unsigned long timeout; @@ -91,7 +90,9 @@ int __cpuinit platform_boot_secondary(unsigned int cpu, struct task_struct *idle SSYNC(); } - timeout = jiffies + 1 * HZ; + timeout = jiffies + HZ; + /* release the lock and let coreb run */ + spin_unlock(&boot_lock); while (time_before(jiffies, timeout)) { if (cpu_online(cpu)) break; @@ -100,8 +101,6 @@ int __cpuinit platform_boot_secondary(unsigned int cpu, struct task_struct *idle } if (cpu_online(cpu)) { - /* release the lock and let coreb run */ - spin_unlock(&boot_lock); return 0; } else panic("CPU%u: processor failed to boot\n", cpu); @@ -155,7 +154,7 @@ void platform_clear_ipi(unsigned int cpu, int irq) * Setup core B's local core timer. * In SMP, core timer is used for clock event device. */ -void __cpuinit bfin_local_timer_setup(void) +void bfin_local_timer_setup(void) { #if defined(CONFIG_TICKSOURCE_CORETMR) struct irq_data *data = irq_get_irq_data(IRQ_CORETMR); diff --git a/arch/blackfin/mach-bf609/Kconfig b/arch/blackfin/mach-bf609/Kconfig index 95a4f1b..2bcbf94 100644 --- a/arch/blackfin/mach-bf609/Kconfig +++ b/arch/blackfin/mach-bf609/Kconfig @@ -59,6 +59,1661 @@ config SEC_IRQ_PRIORITY_LEVELS Divide the total number of interrupt priority levels into sub-levels. There is 2 ^ (SEC_IRQ_PRIORITY_LEVELS + 1) different levels. + +comment "System Cross Bar Priority Assignment" + +config SCB_PRIORITY + bool "Init System Cross Bar Priority" + default n + +menuconfig SCB0_MI0 + bool "SCB0 Master Interface 0 (DDR)" + default n + depends on SCB_PRIORITY + help + The slave interface id of each slot should be set according following table. + Core 0 -- 0 + Core 1 -- 2 + SCB1 -- 9 + SCB2 -- 10 + SCB3 -- 11 + SCB4 -- 12 + SCB5 -- 5 + SCB6 -- 6 + SCB7 -- 8 + SCB8 -- 7 + SCB9 -- 4 + USB -- 13 + +if SCB0_MI0 + +config SCB0_MI0_SLOT0 + int "Slot 0 slave interface id" + default 0 + range 0 13 + +config SCB0_MI0_SLOT1 + int "Slot 1 slave interface id" + default 2 + range 0 13 + +config SCB0_MI0_SLOT2 + int "Slot 2 slave interface id" + default 4 + range 0 13 + +config SCB0_MI0_SLOT3 + int "Slot 3 slave interface id" + default 5 + range 0 13 + +config SCB0_MI0_SLOT4 + int "Slot 4 slave interface id" + default 6 + range 0 13 + +config SCB0_MI0_SLOT5 + int "Slot 5 slave interface id" + default 7 + range 0 13 + +config SCB0_MI0_SLOT6 + int "Slot 6 slave interface id" + default 8 + range 0 13 + +config SCB0_MI0_SLOT7 + int "Slot 7 slave interface id" + default 9 + range 0 13 + +config SCB0_MI0_SLOT8 + int "Slot 8 slave interface id" + default 10 + range 0 13 + +config SCB0_MI0_SLOT9 + int "Slot 9 slave interface id" + default 11 + range 0 13 + +config SCB0_MI0_SLOT10 + int "Slot 10 slave interface id" + default 13 + range 0 13 + +config SCB0_MI0_SLOT11 + int "Slot 11 slave interface id" + default 12 + range 0 13 + +config SCB0_MI0_SLOT12 + int "Slot 12 slave interface id" + default 0 + range 0 13 + +config SCB0_MI0_SLOT13 + int "Slot 13 slave interface id" + default 2 + range 0 13 + +config SCB0_MI0_SLOT14 + int "Slot 14 slave interface id" + default 4 + range 0 13 + +config SCB0_MI0_SLOT15 + int "Slot 15 slave interface id" + default 5 + range 0 13 + +config SCB0_MI0_SLOT16 + int "Slot 16 slave interface id" + default 6 + range 0 13 + +config SCB0_MI0_SLOT17 + int "Slot 17 slave interface id" + default 7 + range 0 13 + +config SCB0_MI0_SLOT18 + int "Slot 18 slave interface id" + default 8 + range 0 13 + +config SCB0_MI0_SLOT19 + int "Slot 19 slave interface id" + default 9 + range 0 13 + +config SCB0_MI0_SLOT20 + int "Slot 20 slave interface id" + default 10 + range 0 13 + +config SCB0_MI0_SLOT21 + int "Slot 21 slave interface id" + default 11 + range 0 13 + +config SCB0_MI0_SLOT22 + int "Slot 22 slave interface id" + default 13 + range 0 13 + +config SCB0_MI0_SLOT23 + int "Slot 23 slave interface id" + default 12 + range 0 13 + +config SCB0_MI0_SLOT24 + int "Slot 24 slave interface id" + default 0 + range 0 13 + +config SCB0_MI0_SLOT25 + int "Slot 25 slave interface id" + default 2 + range 0 13 + +config SCB0_MI0_SLOT26 + int "Slot 26 slave interface id" + default 4 + range 0 13 + +config SCB0_MI0_SLOT27 + int "Slot 27 slave interface id" + default 5 + range 0 13 + +config SCB0_MI0_SLOT28 + int "Slot 28 slave interface id" + default 6 + range 0 13 + +config SCB0_MI0_SLOT29 + int "Slot 29 slave interface id" + default 7 + range 0 13 + +config SCB0_MI0_SLOT30 + int "Slot 30 slave interface id" + default 8 + range 0 13 + +config SCB0_MI0_SLOT31 + int "Slot 31 slave interface id" + default 13 + range 0 13 + +endif # SCB0_MI0 + +menuconfig SCB0_MI1 + bool "SCB0 Master Interface 1 (SMC)" + default n + depends on SCB_PRIORITY + help + The slave interface id of each slot should be set according following table. + Core 0 -- 0 + Core 1 -- 2 + SCB1 -- 9 + SCB2 -- 10 + SCB3 -- 11 + SCB4 -- 12 + SCB5 -- 5 + SCB6 -- 6 + SCB7 -- 8 + SCB8 -- 7 + SCB9 -- 4 + USB -- 13 + +if SCB0_MI1 + +config SCB0_MI1_SLOT0 + int "Slot 0 slave interface id" + default 0 + range 0 13 + +config SCB0_MI1_SLOT1 + int "Slot 1 slave interface id" + default 2 + range 0 13 + +config SCB0_MI1_SLOT2 + int "Slot 2 slave interface id" + default 4 + range 0 13 + +config SCB0_MI1_SLOT3 + int "Slot 3 slave interface id" + default 5 + range 0 13 + +config SCB0_MI1_SLOT4 + int "Slot 4 slave interface id" + default 6 + range 0 13 + +config SCB0_MI1_SLOT5 + int "Slot 5 slave interface id" + default 7 + range 0 13 + +config SCB0_MI1_SLOT6 + int "Slot 6 slave interface id" + default 8 + range 0 13 + +config SCB0_MI1_SLOT7 + int "Slot 7 slave interface id" + default 9 + range 0 13 + +config SCB0_MI1_SLOT8 + int "Slot 8 slave interface id" + default 10 + range 0 13 + +config SCB0_MI1_SLOT9 + int "Slot 9 slave interface id" + default 11 + range 0 13 + +config SCB0_MI1_SLOT10 + int "Slot 10 slave interface id" + default 13 + range 0 13 + +config SCB0_MI1_SLOT11 + int "Slot 11 slave interface id" + default 12 + range 0 13 + +config SCB0_MI1_SLOT12 + int "Slot 12 slave interface id" + default 0 + range 0 13 + +config SCB0_MI1_SLOT13 + int "Slot 13 slave interface id" + default 2 + range 0 13 + +config SCB0_MI1_SLOT14 + int "Slot 14 slave interface id" + default 4 + range 0 13 + +config SCB0_MI1_SLOT15 + int "Slot 15 slave interface id" + default 5 + range 0 13 + +config SCB0_MI1_SLOT16 + int "Slot 16 slave interface id" + default 6 + range 0 13 + +config SCB0_MI1_SLOT17 + int "Slot 17 slave interface id" + default 7 + range 0 13 + +config SCB0_MI1_SLOT18 + int "Slot 18 slave interface id" + default 8 + range 0 13 + +config SCB0_MI1_SLOT19 + int "Slot 19 slave interface id" + default 9 + range 0 13 + +config SCB0_MI1_SLOT20 + int "Slot 20 slave interface id" + default 10 + range 0 13 + +config SCB0_MI1_SLOT21 + int "Slot 21 slave interface id" + default 11 + range 0 13 + +config SCB0_MI1_SLOT22 + int "Slot 22 slave interface id" + default 13 + range 0 13 + +config SCB0_MI1_SLOT23 + int "Slot 23 slave interface id" + default 12 + range 0 13 + +config SCB0_MI1_SLOT24 + int "Slot 24 slave interface id" + default 0 + range 0 13 + +config SCB0_MI1_SLOT25 + int "Slot 25 slave interface id" + default 2 + range 0 13 + +config SCB0_MI1_SLOT26 + int "Slot 26 slave interface id" + default 4 + range 0 13 + +config SCB0_MI1_SLOT27 + int "Slot 27 slave interface id" + default 5 + range 0 13 + +config SCB0_MI1_SLOT28 + int "Slot 28 slave interface id" + default 6 + range 0 13 + +config SCB0_MI1_SLOT29 + int "Slot 29 slave interface id" + default 7 + range 0 13 + +config SCB0_MI1_SLOT30 + int "Slot 30 slave interface id" + default 8 + range 0 13 + +config SCB0_MI1_SLOT31 + int "Slot 31 slave interface id" + default 13 + range 0 13 + +endif # SCB0_MI1 + +menuconfig SCB0_MI2 + bool "SCB0 Master Interface 2 (Data L2)" + default n + depends on SCB_PRIORITY + help + The slave interface id of each slot should be set according following table. + Core 0 -- 0 + Core 1 -- 2 + SCB1 -- 9 + SCB2 -- 10 + SCB3 -- 11 + SCB4 -- 12 + SCB5 -- 5 + SCB6 -- 6 + SCB7 -- 8 + SCB8 -- 7 + SCB9 -- 4 + USB -- 13 + +if SCB0_MI2 + +config SCB0_MI2_SLOT0 + int "Slot 0 slave interface id" + default 4 + range 0 13 + +config SCB0_MI2_SLOT1 + int "Slot 1 slave interface id" + default 5 + range 0 13 + +config SCB0_MI2_SLOT2 + int "Slot 2 slave interface id" + default 6 + range 0 13 + +config SCB0_MI2_SLOT3 + int "Slot 3 slave interface id" + default 7 + range 0 13 + +config SCB0_MI2_SLOT4 + int "Slot 4 slave interface id" + default 8 + range 0 13 + +config SCB0_MI2_SLOT5 + int "Slot 5 slave interface id" + default 9 + range 0 13 + +config SCB0_MI2_SLOT6 + int "Slot 6 slave interface id" + default 10 + range 0 13 + +config SCB0_MI2_SLOT7 + int "Slot 7 slave interface id" + default 11 + range 0 13 + +config SCB0_MI2_SLOT8 + int "Slot 8 slave interface id" + default 13 + range 0 13 + +config SCB0_MI2_SLOT9 + int "Slot 9 slave interface id" + default 12 + range 0 13 + +config SCB0_MI2_SLOT10 + int "Slot 10 slave interface id" + default 4 + range 0 13 + +config SCB0_MI2_SLOT11 + int "Slot 11 slave interface id" + default 5 + range 0 13 + +config SCB0_MI2_SLOT12 + int "Slot 12 slave interface id" + default 6 + range 0 13 + +config SCB0_MI2_SLOT13 + int "Slot 13 slave interface id" + default 7 + range 0 13 + +config SCB0_MI2_SLOT14 + int "Slot 14 slave interface id" + default 8 + range 0 13 + +config SCB0_MI2_SLOT15 + int "Slot 15 slave interface id" + default 9 + range 0 13 + +config SCB0_MI2_SLOT16 + int "Slot 16 slave interface id" + default 10 + range 0 13 + +config SCB0_MI2_SLOT17 + int "Slot 17 slave interface id" + default 11 + range 0 13 + +config SCB0_MI2_SLOT18 + int "Slot 18 slave interface id" + default 13 + range 0 13 + +config SCB0_MI2_SLOT19 + int "Slot 19 slave interface id" + default 12 + range 0 13 + +config SCB0_MI2_SLOT20 + int "Slot 20 slave interface id" + default 4 + range 0 13 + +config SCB0_MI2_SLOT21 + int "Slot 21 slave interface id" + default 5 + range 0 13 + +config SCB0_MI2_SLOT22 + int "Slot 22 slave interface id" + default 6 + range 0 13 + +config SCB0_MI2_SLOT23 + int "Slot 23 slave interface id" + default 7 + range 0 13 + +config SCB0_MI2_SLOT24 + int "Slot 24 slave interface id" + default 8 + range 0 13 + +config SCB0_MI2_SLOT25 + int "Slot 25 slave interface id" + default 9 + range 0 13 + +config SCB0_MI2_SLOT26 + int "Slot 26 slave interface id" + default 10 + range 0 13 + +config SCB0_MI2_SLOT27 + int "Slot 27 slave interface id" + default 11 + range 0 13 + +config SCB0_MI2_SLOT28 + int "Slot 28 slave interface id" + default 13 + range 0 13 + +config SCB0_MI2_SLOT29 + int "Slot 29 slave interface id" + default 12 + range 0 13 + +config SCB0_MI2_SLOT30 + int "Slot 30 slave interface id" + default 4 + range 0 13 + +config SCB0_MI2_SLOT31 + int "Slot 31 slave interface id" + default 7 + range 0 13 + +endif # SCB0_MI2 + +menuconfig SCB0_MI3 + bool "SCB0 Master Interface 3 (L1A)" + default n + depends on SCB_PRIORITY + help + The slave interface id of each slot should be set according following table. + Core 0 -- 0 + Core 1 -- 2 + SCB1 -- 9 + SCB2 -- 10 + SCB3 -- 11 + SCB4 -- 12 + SCB5 -- 5 + SCB6 -- 6 + SCB7 -- 8 + SCB8 -- 7 + SCB9 -- 4 + USB -- 13 + +if SCB0_MI3 + +config SCB0_MI3_SLOT0 + int "Slot 0 slave interface id" + default 4 + range 0 13 + +config SCB0_MI3_SLOT1 + int "Slot 1 slave interface id" + default 5 + range 0 13 + +config SCB0_MI3_SLOT2 + int "Slot 2 slave interface id" + default 6 + range 0 13 + +config SCB0_MI3_SLOT3 + int "Slot 3 slave interface id" + default 7 + range 0 13 + +config SCB0_MI3_SLOT4 + int "Slot 4 slave interface id" + default 8 + range 0 13 + +config SCB0_MI3_SLOT5 + int "Slot 5 slave interface id" + default 9 + range 0 13 + +config SCB0_MI3_SLOT6 + int "Slot 6 slave interface id" + default 10 + range 0 13 + +config SCB0_MI3_SLOT7 + int "Slot 7 slave interface id" + default 11 + range 0 13 + +config SCB0_MI3_SLOT8 + int "Slot 8 slave interface id" + default 13 + range 0 13 + +config SCB0_MI3_SLOT9 + int "Slot 9 slave interface id" + default 12 + range 0 13 + +config SCB0_MI3_SLOT10 + int "Slot 10 slave interface id" + default 4 + range 0 13 + +config SCB0_MI3_SLOT11 + int "Slot 11 slave interface id" + default 5 + range 0 13 + +config SCB0_MI3_SLOT12 + int "Slot 12 slave interface id" + default 6 + range 0 13 + +config SCB0_MI3_SLOT13 + int "Slot 13 slave interface id" + default 7 + range 0 13 + +config SCB0_MI3_SLOT14 + int "Slot 14 slave interface id" + default 8 + range 0 13 + +config SCB0_MI3_SLOT15 + int "Slot 15 slave interface id" + default 9 + range 0 13 + +config SCB0_MI3_SLOT16 + int "Slot 16 slave interface id" + default 10 + range 0 13 + +config SCB0_MI3_SLOT17 + int "Slot 17 slave interface id" + default 11 + range 0 13 + +config SCB0_MI3_SLOT18 + int "Slot 18 slave interface id" + default 13 + range 0 13 + +config SCB0_MI3_SLOT19 + int "Slot 19 slave interface id" + default 12 + range 0 13 + +config SCB0_MI3_SLOT20 + int "Slot 20 slave interface id" + default 4 + range 0 13 + +config SCB0_MI3_SLOT21 + int "Slot 21 slave interface id" + default 5 + range 0 13 + +config SCB0_MI3_SLOT22 + int "Slot 22 slave interface id" + default 6 + range 0 13 + +config SCB0_MI3_SLOT23 + int "Slot 23 slave interface id" + default 7 + range 0 13 + +config SCB0_MI3_SLOT24 + int "Slot 24 slave interface id" + default 8 + range 0 13 + +config SCB0_MI3_SLOT25 + int "Slot 25 slave interface id" + default 9 + range 0 13 + +config SCB0_MI3_SLOT26 + int "Slot 26 slave interface id" + default 10 + range 0 13 + +config SCB0_MI3_SLOT27 + int "Slot 27 slave interface id" + default 11 + range 0 13 + +config SCB0_MI3_SLOT28 + int "Slot 28 slave interface id" + default 13 + range 0 13 + +config SCB0_MI3_SLOT29 + int "Slot 29 slave interface id" + default 12 + range 0 13 + +config SCB0_MI3_SLOT30 + int "Slot 30 slave interface id" + default 4 + range 0 13 + +config SCB0_MI3_SLOT31 + int "Slot 31 slave interface id" + default 7 + range 0 13 + +endif # SCB0_MI3 + +menuconfig SCB0_MI4 + bool "SCB0 Master Interface 4 (L1B)" + default n + depends on SCB_PRIORITY + help + The slave interface id of each slot should be set according following table. + Core 0 -- 0 + Core 1 -- 2 + SCB1 -- 9 + SCB2 -- 10 + SCB3 -- 11 + SCB4 -- 12 + SCB5 -- 5 + SCB6 -- 6 + SCB7 -- 8 + SCB8 -- 7 + SCB9 -- 4 + USB -- 13 + +if SCB0_MI4 + +config SCB0_MI4_SLOT0 + int "Slot 0 slave interface id" + default 4 + range 0 13 + +config SCB0_MI4_SLOT1 + int "Slot 1 slave interface id" + default 5 + range 0 13 + +config SCB0_MI4_SLOT2 + int "Slot 2 slave interface id" + default 6 + range 0 13 + +config SCB0_MI4_SLOT3 + int "Slot 3 slave interface id" + default 7 + range 0 13 + +config SCB0_MI4_SLOT4 + int "Slot 4 slave interface id" + default 8 + range 0 13 + +config SCB0_MI4_SLOT5 + int "Slot 5 slave interface id" + default 9 + range 0 13 + +config SCB0_MI4_SLOT6 + int "Slot 6 slave interface id" + default 10 + range 0 13 + +config SCB0_MI4_SLOT7 + int "Slot 7 slave interface id" + default 11 + range 0 13 + +config SCB0_MI4_SLOT8 + int "Slot 8 slave interface id" + default 13 + range 0 13 + +config SCB0_MI4_SLOT9 + int "Slot 9 slave interface id" + default 12 + range 0 13 + +config SCB0_MI4_SLOT10 + int "Slot 10 slave interface id" + default 4 + range 0 13 + +config SCB0_MI4_SLOT11 + int "Slot 11 slave interface id" + default 5 + range 0 13 + +config SCB0_MI4_SLOT12 + int "Slot 12 slave interface id" + default 6 + range 0 13 + +config SCB0_MI4_SLOT13 + int "Slot 13 slave interface id" + default 7 + range 0 13 + +config SCB0_MI4_SLOT14 + int "Slot 14 slave interface id" + default 8 + range 0 13 + +config SCB0_MI4_SLOT15 + int "Slot 15 slave interface id" + default 9 + range 0 13 + +config SCB0_MI4_SLOT16 + int "Slot 16 slave interface id" + default 10 + range 0 13 + +config SCB0_MI4_SLOT17 + int "Slot 17 slave interface id" + default 11 + range 0 13 + +config SCB0_MI4_SLOT18 + int "Slot 18 slave interface id" + default 13 + range 0 13 + +config SCB0_MI4_SLOT19 + int "Slot 19 slave interface id" + default 12 + range 0 13 + +config SCB0_MI4_SLOT20 + int "Slot 20 slave interface id" + default 4 + range 0 13 + +config SCB0_MI4_SLOT21 + int "Slot 21 slave interface id" + default 5 + range 0 13 + +config SCB0_MI4_SLOT22 + int "Slot 22 slave interface id" + default 6 + range 0 13 + +config SCB0_MI4_SLOT23 + int "Slot 23 slave interface id" + default 7 + range 0 13 + +config SCB0_MI4_SLOT24 + int "Slot 24 slave interface id" + default 8 + range 0 13 + +config SCB0_MI4_SLOT25 + int "Slot 25 slave interface id" + default 9 + range 0 13 + +config SCB0_MI4_SLOT26 + int "Slot 26 slave interface id" + default 10 + range 0 13 + +config SCB0_MI4_SLOT27 + int "Slot 27 slave interface id" + default 11 + range 0 13 + +config SCB0_MI4_SLOT28 + int "Slot 28 slave interface id" + default 13 + range 0 13 + +config SCB0_MI4_SLOT29 + int "Slot 29 slave interface id" + default 12 + range 0 13 + +config SCB0_MI4_SLOT30 + int "Slot 30 slave interface id" + default 4 + range 0 13 + +config SCB0_MI4_SLOT31 + int "Slot 31 slave interface id" + default 7 + range 0 13 + +endif # SCB0_MI4 + +menuconfig SCB0_MI5 + bool "SCB0 Master Interface 5 (SMMR)" + default n + depends on SCB_PRIORITY + help + The slave interface id of each slot should be set according following table. + MMR0 -- 1 + MMR1 -- 3 + SCB2 -- 10 + SCB4 -- 12 + +if SCB0_MI5 + +config SCB0_MI5_SLOT0 + int "Slot 0 slave interface id" + default 1 + range 0 13 + +config SCB0_MI5_SLOT1 + int "Slot 1 slave interface id" + default 3 + range 0 13 + +config SCB0_MI5_SLOT2 + int "Slot 2 slave interface id" + default 10 + range 0 13 + +config SCB0_MI5_SLOT3 + int "Slot 3 slave interface id" + default 12 + range 0 13 + +config SCB0_MI5_SLOT4 + int "Slot 4 slave interface id" + default 1 + range 0 13 + +config SCB0_MI5_SLOT5 + int "Slot 5 slave interface id" + default 3 + range 0 13 + +config SCB0_MI5_SLOT6 + int "Slot 6 slave interface id" + default 10 + range 0 13 + +config SCB0_MI5_SLOT7 + int "Slot 7 slave interface id" + default 12 + range 0 13 + +config SCB0_MI5_SLOT8 + int "Slot 8 slave interface id" + default 1 + range 0 13 + +config SCB0_MI5_SLOT9 + int "Slot 9 slave interface id" + default 3 + range 0 13 + +config SCB0_MI5_SLOT10 + int "Slot 10 slave interface id" + default 10 + range 0 13 + +config SCB0_MI5_SLOT11 + int "Slot 11 slave interface id" + default 12 + range 0 13 + +config SCB0_MI5_SLOT12 + int "Slot 12 slave interface id" + default 1 + range 0 13 + +config SCB0_MI5_SLOT13 + int "Slot 13 slave interface id" + default 3 + range 0 13 + +config SCB0_MI5_SLOT14 + int "Slot 14 slave interface id" + default 10 + range 0 13 + +config SCB0_MI5_SLOT15 + int "Slot 15 slave interface id" + default 12 + range 0 13 + +endif # SCB0_MI5 + +menuconfig SCB1_MI0 + bool "SCB1 Master Interface 0" + default n + depends on SCB_PRIORITY + help + The slave interface id of each slot should be set according following table. + SPORT0A -- 0 + SPORT0B -- 1 + SPORT1A -- 2 + SPORT1B -- 3 + SPORT2A -- 4 + SPORT2B -- 5 + SPI0TX -- 6 + SPI0RX -- 7 + SPI1TX -- 8 + SPI1RX -- 9 + +if SCB1_MI0 + +config SCB1_MI0_SLOT0 + int "Slot 0 slave interface id" + default 0 + range 0 9 + +config SCB1_MI0_SLOT1 + int "Slot 1 slave interface id" + default 1 + range 0 9 + +config SCB1_MI0_SLOT2 + int "Slot 2 slave interface id" + default 2 + range 0 9 + +config SCB1_MI0_SLOT3 + int "Slot 3 slave interface id" + default 3 + range 0 9 + +config SCB1_MI0_SLOT4 + int "Slot 4 slave interface id" + default 4 + range 0 9 + +config SCB1_MI0_SLOT5 + int "Slot 5 slave interface id" + default 5 + range 0 9 + +config SCB1_MI0_SLOT6 + int "Slot 6 slave interface id" + default 6 + range 0 9 + +config SCB1_MI0_SLOT7 + int "Slot 7 slave interface id" + default 7 + range 0 9 + +config SCB1_MI0_SLOT8 + int "Slot 8 slave interface id" + default 8 + range 0 9 + +config SCB1_MI0_SLOT9 + int "Slot 9 slave interface id" + default 9 + range 0 9 + +config SCB1_MI0_SLOT10 + int "Slot 10 slave interface id" + default 0 + range 0 9 + +config SCB1_MI0_SLOT11 + int "Slot 11 slave interface id" + default 1 + range 0 9 + +config SCB1_MI0_SLOT12 + int "Slot 12 slave interface id" + default 2 + range 0 9 + +config SCB1_MI0_SLOT13 + int "Slot 13 slave interface id" + default 3 + range 0 9 + +config SCB1_MI0_SLOT14 + int "Slot 14 slave interface id" + default 4 + range 0 9 + +config SCB1_MI0_SLOT15 + int "Slot 15 slave interface id" + default 5 + range 0 9 + +config SCB1_MI0_SLOT16 + int "Slot 16 slave interface id" + default 6 + range 0 13 + +config SCB1_MI0_SLOT17 + int "Slot 17 slave interface id" + default 7 + range 0 13 + +config SCB1_MI0_SLOT18 + int "Slot 18 slave interface id" + default 8 + range 0 13 + +config SCB1_MI0_SLOT19 + int "Slot 19 slave interface id" + default 9 + range 0 13 + +endif # SCB1_MI0 + +menuconfig SCB2_MI0 + bool "SCB2 Master Interface 0" + default n + depends on SCB_PRIORITY + help + The slave interface id of each slot should be set according following table. + RSI -- 0 + SDU DMA -- 1 + SDU -- 2 + EMAC0 -- 3 + EMAC1 -- 4 + +if SCB2_MI0 + +config SCB2_MI0_SLOT0 + int "Slot 0 slave interface id" + default 0 + range 0 4 + +config SCB2_MI0_SLOT1 + int "Slot 1 slave interface id" + default 1 + range 0 4 + +config SCB2_MI0_SLOT2 + int "Slot 2 slave interface id" + default 2 + range 0 4 + +config SCB2_MI0_SLOT3 + int "Slot 3 slave interface id" + default 3 + range 0 4 + +config SCB2_MI0_SLOT4 + int "Slot 4 slave interface id" + default 4 + range 0 4 + +config SCB2_MI0_SLOT5 + int "Slot 5 slave interface id" + default 0 + range 0 4 + +config SCB2_MI0_SLOT6 + int "Slot 6 slave interface id" + default 1 + range 0 4 + +config SCB2_MI0_SLOT7 + int "Slot 7 slave interface id" + default 2 + range 0 4 + +config SCB2_MI0_SLOT8 + int "Slot 8 slave interface id" + default 3 + range 0 4 + +config SCB2_MI0_SLOT9 + int "Slot 9 slave interface id" + default 4 + range 0 4 + +endif # SCB2_MI0 + +menuconfig SCB3_MI0 + bool "SCB3 Master Interface 0" + default n + depends on SCB_PRIORITY + help + The slave interface id of each slot should be set according following table. + LP0 -- 0 + LP1 -- 1 + LP2 -- 2 + LP3 -- 3 + UART0TX -- 4 + UART0RX -- 5 + UART1TX -- 4 + UART1RX -- 5 + +if SCB3_MI0 + +config SCB3_MI0_SLOT0 + int "Slot 0 slave interface id" + default 0 + range 0 7 + +config SCB3_MI0_SLOT1 + int "Slot 1 slave interface id" + default 1 + range 0 7 + +config SCB3_MI0_SLOT2 + int "Slot 2 slave interface id" + default 2 + range 0 7 + +config SCB3_MI0_SLOT3 + int "Slot 3 slave interface id" + default 3 + range 0 7 + +config SCB3_MI0_SLOT4 + int "Slot 4 slave interface id" + default 4 + range 0 7 + +config SCB3_MI0_SLOT5 + int "Slot 5 slave interface id" + default 5 + range 0 7 + +config SCB3_MI0_SLOT6 + int "Slot 6 slave interface id" + default 6 + range 0 7 + +config SCB3_MI0_SLOT7 + int "Slot 7 slave interface id" + default 7 + range 0 7 + +config SCB3_MI0_SLOT8 + int "Slot 8 slave interface id" + default 0 + range 0 7 + +config SCB3_MI0_SLOT9 + int "Slot 9 slave interface id" + default 1 + range 0 7 + +config SCB3_MI0_SLOT10 + int "Slot 10 slave interface id" + default 2 + range 0 7 + +config SCB3_MI0_SLOT11 + int "Slot 11 slave interface id" + default 3 + range 0 7 + +config SCB3_MI0_SLOT12 + int "Slot 12 slave interface id" + default 4 + range 0 7 + +config SCB3_MI0_SLOT13 + int "Slot 13 slave interface id" + default 5 + range 0 7 + +config SCB3_MI0_SLOT14 + int "Slot 14 slave interface id" + default 6 + range 0 7 + +config SCB3_MI0_SLOT15 + int "Slot 15 slave interface id" + default 7 + range 0 7 + +endif # SCB3_MI0 + +menuconfig SCB4_MI0 + bool "SCB4 Master Interface 0" + default n + depends on SCB_PRIORITY + help + The slave interface id of each slot should be set according following table. + MDA21 -- 0 + MDA22 -- 1 + MDA23 -- 2 + MDA24 -- 3 + MDA25 -- 4 + MDA26 -- 5 + MDA27 -- 6 + MDA28 -- 7 + +if SCB4_MI0 + +config SCB4_MI0_SLOT0 + int "Slot 0 slave interface id" + default 0 + range 0 7 + +config SCB4_MI0_SLOT1 + int "Slot 1 slave interface id" + default 1 + range 0 7 + +config SCB4_MI0_SLOT2 + int "Slot 2 slave interface id" + default 2 + range 0 7 + +config SCB4_MI0_SLOT3 + int "Slot 3 slave interface id" + default 3 + range 0 7 + +config SCB4_MI0_SLOT4 + int "Slot 4 slave interface id" + default 4 + range 0 7 + +config SCB4_MI0_SLOT5 + int "Slot 5 slave interface id" + default 5 + range 0 7 + +config SCB4_MI0_SLOT6 + int "Slot 6 slave interface id" + default 6 + range 0 7 + +config SCB4_MI0_SLOT7 + int "Slot 7 slave interface id" + default 7 + range 0 7 + +config SCB4_MI0_SLOT8 + int "Slot 8 slave interface id" + default 0 + range 0 7 + +config SCB4_MI0_SLOT9 + int "Slot 9 slave interface id" + default 1 + range 0 7 + +config SCB4_MI0_SLOT10 + int "Slot 10 slave interface id" + default 2 + range 0 7 + +config SCB4_MI0_SLOT11 + int "Slot 11 slave interface id" + default 3 + range 0 7 + +config SCB4_MI0_SLOT12 + int "Slot 12 slave interface id" + default 4 + range 0 7 + +config SCB4_MI0_SLOT13 + int "Slot 13 slave interface id" + default 5 + range 0 7 + +config SCB4_MI0_SLOT14 + int "Slot 14 slave interface id" + default 6 + range 0 7 + +config SCB4_MI0_SLOT15 + int "Slot 15 slave interface id" + default 7 + range 0 7 + +endif # SCB4_MI0 + +menuconfig SCB5_MI0 + bool "SCB5 Master Interface 0" + default n + depends on SCB_PRIORITY + help + The slave interface id of each slot should be set according following table. + PPI0 MDA29 -- 0 + PPI0 MDA30 -- 1 + PPI2 MDA31 -- 2 + PPI2 MDA32 -- 3 + +if SCB5_MI0 + +config SCB5_MI0_SLOT0 + int "Slot 0 slave interface id" + default 0 + range 0 3 + +config SCB5_MI0_SLOT1 + int "Slot 1 slave interface id" + default 1 + range 0 3 + +config SCB5_MI0_SLOT2 + int "Slot 2 slave interface id" + default 2 + range 0 3 + +config SCB5_MI0_SLOT3 + int "Slot 3 slave interface id" + default 3 + range 0 3 + +config SCB5_MI0_SLOT4 + int "Slot 4 slave interface id" + default 0 + range 0 3 + +config SCB5_MI0_SLOT5 + int "Slot 5 slave interface id" + default 1 + range 0 3 + +config SCB5_MI0_SLOT6 + int "Slot 6 slave interface id" + default 2 + range 0 3 + +config SCB5_MI0_SLOT7 + int "Slot 7 slave interface id" + default 3 + range 0 3 + +endif # SCB5_MI0 + +menuconfig SCB6_MI0 + bool "SCB6 Master Interface 0" + default n + depends on SCB_PRIORITY + help + The slave interface id of each slot should be set according following table. + PPI1 MDA33 -- 0 + PPI1 MDA34 -- 1 + +if SCB6_MI0 + +config SCB6_MI0_SLOT0 + int "Slot 0 slave interface id" + default 0 + range 0 1 + +config SCB6_MI0_SLOT1 + int "Slot 1 slave interface id" + default 1 + range 0 1 + +config SCB6_MI0_SLOT2 + int "Slot 2 slave interface id" + default 0 + range 0 1 + +config SCB6_MI0_SLOT3 + int "Slot 3 slave interface id" + default 1 + range 0 1 + +endif # SCB6_MI0 + +menuconfig SCB7_MI0 + bool "SCB7 Master Interface 0" + default n + depends on SCB_PRIORITY + help + The slave interface id of each slot should be set according following table. + PIXC0 -- 0 + PIXC1 -- 1 + PIXC2 -- 2 + +if SCB7_MI0 + +config SCB7_MI0_SLOT0 + int "Slot 0 slave interface id" + default 0 + range 0 2 + +config SCB7_MI0_SLOT1 + int "Slot 1 slave interface id" + default 1 + range 0 2 + +config SCB7_MI0_SLOT2 + int "Slot 2 slave interface id" + default 2 + range 0 2 + +config SCB7_MI0_SLOT3 + int "Slot 3 slave interface id" + default 0 + range 0 2 + +config SCB7_MI0_SLOT4 + int "Slot 4 slave interface id" + default 1 + range 0 2 + +config SCB7_MI0_SLOT5 + int "Slot 5 slave interface id" + default 2 + range 0 2 + +endif # SCB7_MI0 + +menuconfig SCB8_MI0 + bool "SCB8 Master Interface 0" + default n + depends on SCB_PRIORITY + help + The slave interface id of each slot should be set according following table. + PVP CPDOB -- 0 + PVP CPDOC -- 1 + PVP CPCO -- 2 + PVP CPCI -- 3 + +if SCB8_MI0 + +config SCB8_MI0_SLOT0 + int "Slot 0 slave interface id" + default 0 + range 0 3 + +config SCB8_MI0_SLOT1 + int "Slot 1 slave interface id" + default 1 + range 0 3 + +config SCB8_MI0_SLOT2 + int "Slot 2 slave interface id" + default 2 + range 0 3 + +config SCB8_MI0_SLOT3 + int "Slot 3 slave interface id" + default 3 + range 0 3 + +config SCB8_MI0_SLOT4 + int "Slot 4 slave interface id" + default 0 + range 0 3 + +config SCB8_MI0_SLOT5 + int "Slot 5 slave interface id" + default 1 + range 0 3 + +config SCB8_MI0_SLOT6 + int "Slot 6 slave interface id" + default 2 + range 0 3 + +config SCB8_MI0_SLOT7 + int "Slot 7 slave interface id" + default 3 + range 0 3 + +endif # SCB8_MI0 + +menuconfig SCB9_MI0 + bool "SCB9 Master Interface 0" + default n + depends on SCB_PRIORITY + help + The slave interface id of each slot should be set according following table. + PVP MPDO -- 0 + PVP MPDI -- 1 + PVP MPCO -- 2 + PVP MPCI -- 3 + PVP CPDOA -- 4 + +if SCB9_MI0 + +config SCB9_MI0_SLOT0 + int "Slot 0 slave interface id" + default 0 + range 0 4 + +config SCB9_MI0_SLOT1 + int "Slot 1 slave interface id" + default 1 + range 0 4 + +config SCB9_MI0_SLOT2 + int "Slot 2 slave interface id" + default 2 + range 0 4 + +config SCB9_MI0_SLOT3 + int "Slot 3 slave interface id" + default 3 + range 0 4 + +config SCB9_MI0_SLOT4 + int "Slot 4 slave interface id" + default 4 + range 0 4 + +config SCB9_MI0_SLOT5 + int "Slot 5 slave interface id" + default 0 + range 0 4 + +config SCB9_MI0_SLOT6 + int "Slot 6 slave interface id" + default 1 + range 0 4 + +config SCB9_MI0_SLOT7 + int "Slot 7 slave interface id" + default 2 + range 0 4 + +config SCB9_MI0_SLOT8 + int "Slot 8 slave interface id" + default 3 + range 0 4 + +config SCB9_MI0_SLOT9 + int "Slot 9 slave interface id" + default 4 + range 0 4 + +endif # SCB9_MI0 + endmenu endif diff --git a/arch/blackfin/mach-bf609/Makefile b/arch/blackfin/mach-bf609/Makefile index 234fe1b..60ffaf8 100644 --- a/arch/blackfin/mach-bf609/Makefile +++ b/arch/blackfin/mach-bf609/Makefile @@ -4,3 +4,4 @@ obj-y := dma.o clock.o ints-priority.o obj-$(CONFIG_PM) += pm.o dpm.o +obj-$(CONFIG_SCB_PRIORITY) += scb.o diff --git a/arch/blackfin/mach-bf609/boards/ezkit.c b/arch/blackfin/mach-bf609/boards/ezkit.c index 97d7016..d56a55a 100644 --- a/arch/blackfin/mach-bf609/boards/ezkit.c +++ b/arch/blackfin/mach-bf609/boards/ezkit.c @@ -17,7 +17,7 @@ #include <linux/i2c.h> #include <linux/interrupt.h> #include <linux/usb/musb.h> -#include <asm/bfin6xx_spi.h> +#include <asm/bfin_spi3.h> #include <asm/dma.h> #include <asm/gpio.h> #include <asm/nand.h> @@ -104,19 +104,34 @@ static struct platform_device bfin_rotary_device = { #if defined(CONFIG_STMMAC_ETH) || defined(CONFIG_STMMAC_ETH_MODULE) #include <linux/stmmac.h> +#include <linux/phy.h> static unsigned short pins[] = P_RMII0; static struct stmmac_mdio_bus_data phy_private_data = { - .bus_id = 0, .phy_mask = 1, }; +static struct stmmac_dma_cfg eth_dma_cfg = { + .pbl = 2, +}; + +int stmmac_ptp_clk_init(struct platform_device *pdev) +{ + bfin_write32(PADS0_EMAC_PTP_CLKSEL, 0); + return 0; +} + static struct plat_stmmacenet_data eth_private_data = { + .has_gmac = 1, .bus_id = 0, .enh_desc = 1, .phy_addr = 1, .mdio_bus_data = &phy_private_data, + .dma_cfg = ð_dma_cfg, + .force_thresh_dma_mode = 1, + .interface = PHY_INTERFACE_MODE_RMII, + .init = stmmac_ptp_clk_init, }; static struct platform_device bfin_eth_device = { @@ -745,13 +760,13 @@ static struct flash_platform_data bfin_spi_flash_data = { .type = "w25q32", }; -static struct bfin6xx_spi_chip spi_flash_chip_info = { +static struct bfin_spi3_chip spi_flash_chip_info = { .enable_dma = true, /* use dma transfer with this chip*/ }; #endif #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) -static struct bfin6xx_spi_chip spidev_chip_info = { +static struct bfin_spi3_chip spidev_chip_info = { .enable_dma = true, }; #endif @@ -821,7 +836,7 @@ static struct platform_device bfin_i2s = { #if defined(CONFIG_SND_BF5XX_SOC_AD1836) \ || defined(CONFIG_SND_BF5XX_SOC_AD1836_MODULE) static const char * const ad1836_link[] = { - "bfin-tdm.0", + "bfin-i2s.0", "spi0.76", }; static struct platform_device bfin_ad1836_machine = { @@ -1108,6 +1123,81 @@ static struct bfin_display_config bfin_display_data = { }; #endif +#if IS_ENABLED(CONFIG_VIDEO_ADV7343) +#include <media/adv7343.h> + +static struct v4l2_output adv7343_outputs[] = { + { + .index = 0, + .name = "Composite", + .type = V4L2_OUTPUT_TYPE_ANALOG, + .std = V4L2_STD_ALL, + .capabilities = V4L2_OUT_CAP_STD, + }, + { + .index = 1, + .name = "S-Video", + .type = V4L2_OUTPUT_TYPE_ANALOG, + .std = V4L2_STD_ALL, + .capabilities = V4L2_OUT_CAP_STD, + }, + { + .index = 2, + .name = "Component", + .type = V4L2_OUTPUT_TYPE_ANALOG, + .std = V4L2_STD_ALL, + .capabilities = V4L2_OUT_CAP_STD, + }, + +}; + +static struct disp_route adv7343_routes[] = { + { + .output = ADV7343_COMPOSITE_ID, + }, + { + .output = ADV7343_SVIDEO_ID, + }, + { + .output = ADV7343_COMPONENT_ID, + }, +}; + +static struct adv7343_platform_data adv7343_data = { + .mode_config = { + .sleep_mode = false, + .pll_control = false, + .dac_1 = true, + .dac_2 = true, + .dac_3 = true, + .dac_4 = true, + .dac_5 = true, + .dac_6 = true, + }, + .sd_config = { + .sd_dac_out1 = false, + .sd_dac_out2 = false, + }, +}; + +static struct bfin_display_config bfin_display_data = { + .card_name = "BF609", + .outputs = adv7343_outputs, + .num_outputs = ARRAY_SIZE(adv7343_outputs), + .routes = adv7343_routes, + .i2c_adapter_id = 0, + .board_info = { + .type = "adv7343", + .addr = 0x2b, + .platform_data = (void *)&adv7343_data, + }, + .ppi_info = &ppi_info_disp, + .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FS1LO_FS2LO + | EPPI_CTL_POLC3 | EPPI_CTL_BLANKGEN | EPPI_CTL_SYNC2 + | EPPI_CTL_NON656 | EPPI_CTL_DIR), +}; +#endif + static struct platform_device bfin_display_device = { .name = "bfin_display", .dev = { @@ -1296,7 +1386,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { }, #endif }; -#if defined(CONFIG_SPI_BFIN6XX) || defined(CONFIG_SPI_BFIN6XX_MODULE) +#if IS_ENABLED(CONFIG_SPI_BFIN_V3) /* SPI (0) */ static struct resource bfin_spi0_resource[] = { { @@ -1337,13 +1427,13 @@ static struct resource bfin_spi1_resource[] = { }; /* SPI controller data */ -static struct bfin6xx_spi_master bf60x_spi_master_info0 = { +static struct bfin_spi3_master bf60x_spi_master_info0 = { .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS, .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, }; static struct platform_device bf60x_spi_master0 = { - .name = "bfin-spi", + .name = "bfin-spi3", .id = 0, /* Bus number */ .num_resources = ARRAY_SIZE(bfin_spi0_resource), .resource = bfin_spi0_resource, @@ -1352,13 +1442,13 @@ static struct platform_device bf60x_spi_master0 = { }, }; -static struct bfin6xx_spi_master bf60x_spi_master_info1 = { +static struct bfin_spi3_master bf60x_spi_master_info1 = { .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS, .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0}, }; static struct platform_device bf60x_spi_master1 = { - .name = "bfin-spi", + .name = "bfin-spi3", .id = 1, /* Bus number */ .num_resources = ARRAY_SIZE(bfin_spi1_resource), .resource = bfin_spi1_resource, @@ -1534,7 +1624,7 @@ static struct platform_device *ezkit_devices[] __initdata = { &bfin_sdh_device, #endif -#if defined(CONFIG_SPI_BFIN6XX) || defined(CONFIG_SPI_BFIN6XX_MODULE) +#if IS_ENABLED(CONFIG_SPI_BFIN_V3) &bf60x_spi_master0, &bf60x_spi_master1, #endif diff --git a/arch/blackfin/mach-bf609/clock.c b/arch/blackfin/mach-bf609/clock.c index 437d56c..dab8849 100644 --- a/arch/blackfin/mach-bf609/clock.c +++ b/arch/blackfin/mach-bf609/clock.c @@ -220,6 +220,12 @@ unsigned long sys_clk_get_rate(struct clk *clk) } } +unsigned long dummy_get_rate(struct clk *clk) +{ + clk->parent->rate = clk_get_rate(clk->parent); + return clk->parent->rate; +} + unsigned long sys_clk_round_rate(struct clk *clk, unsigned long rate) { unsigned long max_rate; @@ -283,6 +289,10 @@ static struct clk_ops sys_clk_ops = { .round_rate = sys_clk_round_rate, }; +static struct clk_ops dummy_clk_ops = { + .get_rate = dummy_get_rate, +}; + static struct clk sys_clkin = { .name = "SYS_CLKIN", .rate = CONFIG_CLKIN_HZ, @@ -364,6 +374,12 @@ static struct clk oclk = { .parent = &pll_clk, }; +static struct clk ethclk = { + .name = "stmmaceth", + .parent = &sclk0, + .ops = &dummy_clk_ops, +}; + static struct clk_lookup bf609_clks[] = { CLK(sys_clkin, NULL, "SYS_CLKIN"), CLK(pll_clk, NULL, "PLLCLK"), @@ -375,6 +391,7 @@ static struct clk_lookup bf609_clks[] = { CLK(sclk1, NULL, "SCLK1"), CLK(dclk, NULL, "DCLK"), CLK(oclk, NULL, "OCLK"), + CLK(ethclk, NULL, "stmmaceth"), }; int __init clk_init(void) diff --git a/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h b/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h index f1a6afa..35caa7b 100644 --- a/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h +++ b/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h @@ -839,6 +839,16 @@ #define PORTG_LOCK 0xFFC03344 /* PORTG Port x GPIO Lock Register */ #define PORTG_REVID 0xFFC0337C /* PORTG Port x GPIO Revision ID */ +/* ================================================== + Pads Controller Registers + ================================================== */ + +/* ========================= + PADS0 + ========================= */ +#define PADS0_EMAC_PTP_CLKSEL 0xFFC03404 /* PADS0 Clock Selection for EMAC and PTP */ +#define PADS0_TWI_VSEL 0xFFC03408 /* PADS0 TWI Voltage Selection */ +#define PADS0_PORTS_HYST 0xFFC03440 /* PADS0 Hysteresis Enable Register */ /* ========================= PINT Registers diff --git a/arch/blackfin/mach-bf609/scb.c b/arch/blackfin/mach-bf609/scb.c new file mode 100644 index 0000000..ac1f07c --- /dev/null +++ b/arch/blackfin/mach-bf609/scb.c @@ -0,0 +1,363 @@ +/* + * arch/blackfin/mach-common/scb-init.c - reprogram system cross bar priority + * + * Copyright 2012 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include <asm/blackfin.h> +#include <asm/scb.h> + +struct scb_mi_prio scb_data[] = { +#ifdef CONFIG_SCB0_MI0 + { REG_SCB0_ARBR0, REG_SCB0_ARBW0, 32, { + CONFIG_SCB0_MI0_SLOT0, + CONFIG_SCB0_MI0_SLOT1, + CONFIG_SCB0_MI0_SLOT2, + CONFIG_SCB0_MI0_SLOT3, + CONFIG_SCB0_MI0_SLOT4, + CONFIG_SCB0_MI0_SLOT5, + CONFIG_SCB0_MI0_SLOT6, + CONFIG_SCB0_MI0_SLOT7, + CONFIG_SCB0_MI0_SLOT8, + CONFIG_SCB0_MI0_SLOT9, + CONFIG_SCB0_MI0_SLOT10, + CONFIG_SCB0_MI0_SLOT11, + CONFIG_SCB0_MI0_SLOT12, + CONFIG_SCB0_MI0_SLOT13, + CONFIG_SCB0_MI0_SLOT14, + CONFIG_SCB0_MI0_SLOT15, + CONFIG_SCB0_MI0_SLOT16, + CONFIG_SCB0_MI0_SLOT17, + CONFIG_SCB0_MI0_SLOT18, + CONFIG_SCB0_MI0_SLOT19, + CONFIG_SCB0_MI0_SLOT20, + CONFIG_SCB0_MI0_SLOT21, + CONFIG_SCB0_MI0_SLOT22, + CONFIG_SCB0_MI0_SLOT23, + CONFIG_SCB0_MI0_SLOT24, + CONFIG_SCB0_MI0_SLOT25, + CONFIG_SCB0_MI0_SLOT26, + CONFIG_SCB0_MI0_SLOT27, + CONFIG_SCB0_MI0_SLOT28, + CONFIG_SCB0_MI0_SLOT29, + CONFIG_SCB0_MI0_SLOT30, + CONFIG_SCB0_MI0_SLOT31 + }, + }, +#endif +#ifdef CONFIG_SCB0_MI1 + { REG_SCB0_ARBR1, REG_SCB0_ARBW1, 32, { + CONFIG_SCB0_MI1_SLOT0, + CONFIG_SCB0_MI1_SLOT1, + CONFIG_SCB0_MI1_SLOT2, + CONFIG_SCB0_MI1_SLOT3, + CONFIG_SCB0_MI1_SLOT4, + CONFIG_SCB0_MI1_SLOT5, + CONFIG_SCB0_MI1_SLOT6, + CONFIG_SCB0_MI1_SLOT7, + CONFIG_SCB0_MI1_SLOT8, + CONFIG_SCB0_MI1_SLOT9, + CONFIG_SCB0_MI1_SLOT10, + CONFIG_SCB0_MI1_SLOT11, + CONFIG_SCB0_MI1_SLOT12, + CONFIG_SCB0_MI1_SLOT13, + CONFIG_SCB0_MI1_SLOT14, + CONFIG_SCB0_MI1_SLOT15, + CONFIG_SCB0_MI1_SLOT16, + CONFIG_SCB0_MI1_SLOT17, + CONFIG_SCB0_MI1_SLOT18, + CONFIG_SCB0_MI1_SLOT19, + CONFIG_SCB0_MI1_SLOT20, + CONFIG_SCB0_MI1_SLOT21, + CONFIG_SCB0_MI1_SLOT22, + CONFIG_SCB0_MI1_SLOT23, + CONFIG_SCB0_MI1_SLOT24, + CONFIG_SCB0_MI1_SLOT25, + CONFIG_SCB0_MI1_SLOT26, + CONFIG_SCB0_MI1_SLOT27, + CONFIG_SCB0_MI1_SLOT28, + CONFIG_SCB0_MI1_SLOT29, + CONFIG_SCB0_MI1_SLOT30, + CONFIG_SCB0_MI1_SLOT31 + }, + }, +#endif +#ifdef CONFIG_SCB0_MI2 + { REG_SCB0_ARBR2, REG_SCB0_ARBW2, 32, { + CONFIG_SCB0_MI2_SLOT0, + CONFIG_SCB0_MI2_SLOT1, + CONFIG_SCB0_MI2_SLOT2, + CONFIG_SCB0_MI2_SLOT3, + CONFIG_SCB0_MI2_SLOT4, + CONFIG_SCB0_MI2_SLOT5, + CONFIG_SCB0_MI2_SLOT6, + CONFIG_SCB0_MI2_SLOT7, + CONFIG_SCB0_MI2_SLOT8, + CONFIG_SCB0_MI2_SLOT9, + CONFIG_SCB0_MI2_SLOT10, + CONFIG_SCB0_MI2_SLOT11, + CONFIG_SCB0_MI2_SLOT12, + CONFIG_SCB0_MI2_SLOT13, + CONFIG_SCB0_MI2_SLOT14, + CONFIG_SCB0_MI2_SLOT15, + CONFIG_SCB0_MI2_SLOT16, + CONFIG_SCB0_MI2_SLOT17, + CONFIG_SCB0_MI2_SLOT18, + CONFIG_SCB0_MI2_SLOT19, + CONFIG_SCB0_MI2_SLOT20, + CONFIG_SCB0_MI2_SLOT21, + CONFIG_SCB0_MI2_SLOT22, + CONFIG_SCB0_MI2_SLOT23, + CONFIG_SCB0_MI2_SLOT24, + CONFIG_SCB0_MI2_SLOT25, + CONFIG_SCB0_MI2_SLOT26, + CONFIG_SCB0_MI2_SLOT27, + CONFIG_SCB0_MI2_SLOT28, + CONFIG_SCB0_MI2_SLOT29, + CONFIG_SCB0_MI2_SLOT30, + CONFIG_SCB0_MI2_SLOT31 + }, + }, +#endif +#ifdef CONFIG_SCB0_MI3 + { REG_SCB0_ARBR3, REG_SCB0_ARBW3, 32, { + CONFIG_SCB0_MI3_SLOT0, + CONFIG_SCB0_MI3_SLOT1, + CONFIG_SCB0_MI3_SLOT2, + CONFIG_SCB0_MI3_SLOT3, + CONFIG_SCB0_MI3_SLOT4, + CONFIG_SCB0_MI3_SLOT5, + CONFIG_SCB0_MI3_SLOT6, + CONFIG_SCB0_MI3_SLOT7, + CONFIG_SCB0_MI3_SLOT8, + CONFIG_SCB0_MI3_SLOT9, + CONFIG_SCB0_MI3_SLOT10, + CONFIG_SCB0_MI3_SLOT11, + CONFIG_SCB0_MI3_SLOT12, + CONFIG_SCB0_MI3_SLOT13, + CONFIG_SCB0_MI3_SLOT14, + CONFIG_SCB0_MI3_SLOT15, + CONFIG_SCB0_MI3_SLOT16, + CONFIG_SCB0_MI3_SLOT17, + CONFIG_SCB0_MI3_SLOT18, + CONFIG_SCB0_MI3_SLOT19, + CONFIG_SCB0_MI3_SLOT20, + CONFIG_SCB0_MI3_SLOT21, + CONFIG_SCB0_MI3_SLOT22, + CONFIG_SCB0_MI3_SLOT23, + CONFIG_SCB0_MI3_SLOT24, + CONFIG_SCB0_MI3_SLOT25, + CONFIG_SCB0_MI3_SLOT26, + CONFIG_SCB0_MI3_SLOT27, + CONFIG_SCB0_MI3_SLOT28, + CONFIG_SCB0_MI3_SLOT29, + CONFIG_SCB0_MI3_SLOT30, + CONFIG_SCB0_MI3_SLOT31 + }, + }, +#endif +#ifdef CONFIG_SCB0_MI4 + { REG_SCB0_ARBR4, REG_SCB4_ARBW0, 32, { + CONFIG_SCB0_MI4_SLOT0, + CONFIG_SCB0_MI4_SLOT1, + CONFIG_SCB0_MI4_SLOT2, + CONFIG_SCB0_MI4_SLOT3, + CONFIG_SCB0_MI4_SLOT4, + CONFIG_SCB0_MI4_SLOT5, + CONFIG_SCB0_MI4_SLOT6, + CONFIG_SCB0_MI4_SLOT7, + CONFIG_SCB0_MI4_SLOT8, + CONFIG_SCB0_MI4_SLOT9, + CONFIG_SCB0_MI4_SLOT10, + CONFIG_SCB0_MI4_SLOT11, + CONFIG_SCB0_MI4_SLOT12, + CONFIG_SCB0_MI4_SLOT13, + CONFIG_SCB0_MI4_SLOT14, + CONFIG_SCB0_MI4_SLOT15, + CONFIG_SCB0_MI4_SLOT16, + CONFIG_SCB0_MI4_SLOT17, + CONFIG_SCB0_MI4_SLOT18, + CONFIG_SCB0_MI4_SLOT19, + CONFIG_SCB0_MI4_SLOT20, + CONFIG_SCB0_MI4_SLOT21, + CONFIG_SCB0_MI4_SLOT22, + CONFIG_SCB0_MI4_SLOT23, + CONFIG_SCB0_MI4_SLOT24, + CONFIG_SCB0_MI4_SLOT25, + CONFIG_SCB0_MI4_SLOT26, + CONFIG_SCB0_MI4_SLOT27, + CONFIG_SCB0_MI4_SLOT28, + CONFIG_SCB0_MI4_SLOT29, + CONFIG_SCB0_MI4_SLOT30, + CONFIG_SCB0_MI4_SLOT31 + }, + }, +#endif +#ifdef CONFIG_SCB0_MI5 + { REG_SCB0_ARBR5, REG_SCB0_ARBW5, 16, { + CONFIG_SCB0_MI5_SLOT0, + CONFIG_SCB0_MI5_SLOT1, + CONFIG_SCB0_MI5_SLOT2, + CONFIG_SCB0_MI5_SLOT3, + CONFIG_SCB0_MI5_SLOT4, + CONFIG_SCB0_MI5_SLOT5, + CONFIG_SCB0_MI5_SLOT6, + CONFIG_SCB0_MI5_SLOT7, + CONFIG_SCB0_MI5_SLOT8, + CONFIG_SCB0_MI5_SLOT9, + CONFIG_SCB0_MI5_SLOT10, + CONFIG_SCB0_MI5_SLOT11, + CONFIG_SCB0_MI5_SLOT12, + CONFIG_SCB0_MI5_SLOT13, + CONFIG_SCB0_MI5_SLOT14, + CONFIG_SCB0_MI5_SLOT15 + }, + }, +#endif +#ifdef CONFIG_SCB1_MI0 + { REG_SCB1_ARBR0, REG_SCB1_ARBW0, 20, { + CONFIG_SCB1_MI0_SLOT0, + CONFIG_SCB1_MI0_SLOT1, + CONFIG_SCB1_MI0_SLOT2, + CONFIG_SCB1_MI0_SLOT3, + CONFIG_SCB1_MI0_SLOT4, + CONFIG_SCB1_MI0_SLOT5, + CONFIG_SCB1_MI0_SLOT6, + CONFIG_SCB1_MI0_SLOT7, + CONFIG_SCB1_MI0_SLOT8, + CONFIG_SCB1_MI0_SLOT9, + CONFIG_SCB1_MI0_SLOT10, + CONFIG_SCB1_MI0_SLOT11, + CONFIG_SCB1_MI0_SLOT12, + CONFIG_SCB1_MI0_SLOT13, + CONFIG_SCB1_MI0_SLOT14, + CONFIG_SCB1_MI0_SLOT15, + CONFIG_SCB1_MI0_SLOT16, + CONFIG_SCB1_MI0_SLOT17, + CONFIG_SCB1_MI0_SLOT18, + CONFIG_SCB1_MI0_SLOT19 + }, + }, +#endif +#ifdef CONFIG_SCB2_MI0 + { REG_SCB2_ARBR0, REG_SCB2_ARBW0, 10, { + CONFIG_SCB2_MI0_SLOT0, + CONFIG_SCB2_MI0_SLOT1, + CONFIG_SCB2_MI0_SLOT2, + CONFIG_SCB2_MI0_SLOT3, + CONFIG_SCB2_MI0_SLOT4, + CONFIG_SCB2_MI0_SLOT5, + CONFIG_SCB2_MI0_SLOT6, + CONFIG_SCB2_MI0_SLOT7, + CONFIG_SCB2_MI0_SLOT8, + CONFIG_SCB2_MI0_SLOT9 + }, + }, +#endif +#ifdef CONFIG_SCB3_MI0 + { REG_SCB3_ARBR0, REG_SCB3_ARBW0, 16, { + CONFIG_SCB3_MI0_SLOT0, + CONFIG_SCB3_MI0_SLOT1, + CONFIG_SCB3_MI0_SLOT2, + CONFIG_SCB3_MI0_SLOT3, + CONFIG_SCB3_MI0_SLOT4, + CONFIG_SCB3_MI0_SLOT5, + CONFIG_SCB3_MI0_SLOT6, + CONFIG_SCB3_MI0_SLOT7, + CONFIG_SCB3_MI0_SLOT8, + CONFIG_SCB3_MI0_SLOT9, + CONFIG_SCB3_MI0_SLOT10, + CONFIG_SCB3_MI0_SLOT11, + CONFIG_SCB3_MI0_SLOT12, + CONFIG_SCB3_MI0_SLOT13, + CONFIG_SCB3_MI0_SLOT14, + CONFIG_SCB3_MI0_SLOT15 + }, + }, +#endif +#ifdef CONFIG_SCB4_MI0 + { REG_SCB4_ARBR0, REG_SCB4_ARBW0, 16, { + CONFIG_SCB4_MI0_SLOT0, + CONFIG_SCB4_MI0_SLOT1, + CONFIG_SCB4_MI0_SLOT2, + CONFIG_SCB4_MI0_SLOT3, + CONFIG_SCB4_MI0_SLOT4, + CONFIG_SCB4_MI0_SLOT5, + CONFIG_SCB4_MI0_SLOT6, + CONFIG_SCB4_MI0_SLOT7, + CONFIG_SCB4_MI0_SLOT8, + CONFIG_SCB4_MI0_SLOT9, + CONFIG_SCB4_MI0_SLOT10, + CONFIG_SCB4_MI0_SLOT11, + CONFIG_SCB4_MI0_SLOT12, + CONFIG_SCB4_MI0_SLOT13, + CONFIG_SCB4_MI0_SLOT14, + CONFIG_SCB4_MI0_SLOT15 + }, + }, +#endif +#ifdef CONFIG_SCB5_MI0 + { REG_SCB5_ARBR0, REG_SCB5_ARBW0, 8, { + CONFIG_SCB5_MI0_SLOT0, + CONFIG_SCB5_MI0_SLOT1, + CONFIG_SCB5_MI0_SLOT2, + CONFIG_SCB5_MI0_SLOT3, + CONFIG_SCB5_MI0_SLOT4, + CONFIG_SCB5_MI0_SLOT5, + CONFIG_SCB5_MI0_SLOT6, + CONFIG_SCB5_MI0_SLOT7 + }, + }, +#endif +#ifdef CONFIG_SCB6_MI0 + { REG_SCB6_ARBR0, REG_SCB6_ARBW0, 4, { + CONFIG_SCB6_MI0_SLOT0, + CONFIG_SCB6_MI0_SLOT1, + CONFIG_SCB6_MI0_SLOT2, + CONFIG_SCB6_MI0_SLOT3 + }, + }, +#endif +#ifdef CONFIG_SCB7_MI0 + { REG_SCB7_ARBR0, REG_SCB7_ARBW0, 6, { + CONFIG_SCB7_MI0_SLOT0, + CONFIG_SCB7_MI0_SLOT1, + CONFIG_SCB7_MI0_SLOT2, + CONFIG_SCB7_MI0_SLOT3, + CONFIG_SCB7_MI0_SLOT4, + CONFIG_SCB7_MI0_SLOT5 + }, + }, +#endif +#ifdef CONFIG_SCB8_MI0 + { REG_SCB8_ARBR0, REG_SCB8_ARBW0, 8, { + CONFIG_SCB8_MI0_SLOT0, + CONFIG_SCB8_MI0_SLOT1, + CONFIG_SCB8_MI0_SLOT2, + CONFIG_SCB8_MI0_SLOT3, + CONFIG_SCB8_MI0_SLOT4, + CONFIG_SCB8_MI0_SLOT5, + CONFIG_SCB8_MI0_SLOT6, + CONFIG_SCB8_MI0_SLOT7 + }, + }, +#endif +#ifdef CONFIG_SCB9_MI0 + { REG_SCB9_ARBR0, REG_SCB9_ARBW0, 10, { + CONFIG_SCB9_MI0_SLOT0, + CONFIG_SCB9_MI0_SLOT1, + CONFIG_SCB9_MI0_SLOT2, + CONFIG_SCB9_MI0_SLOT3, + CONFIG_SCB9_MI0_SLOT4, + CONFIG_SCB9_MI0_SLOT5, + CONFIG_SCB9_MI0_SLOT6, + CONFIG_SCB9_MI0_SLOT7, + CONFIG_SCB9_MI0_SLOT8, + CONFIG_SCB9_MI0_SLOT9 + }, + }, +#endif + { 0, } +}; diff --git a/arch/blackfin/mach-common/Makefile b/arch/blackfin/mach-common/Makefile index 675466d..f099792 100644 --- a/arch/blackfin/mach-common/Makefile +++ b/arch/blackfin/mach-common/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_PM) += pm.o ifneq ($(CONFIG_BF60x),y) obj-$(CONFIG_PM) += dpmc_modes.o endif +obj-$(CONFIG_SCB_PRIORITY) += scb-init.o obj-$(CONFIG_CPU_VOLTAGE) += dpmc.o obj-$(CONFIG_SMP) += smp.o obj-$(CONFIG_BFIN_KERNEL_CLOCK) += clocks-init.o diff --git a/arch/blackfin/mach-common/cache-c.c b/arch/blackfin/mach-common/cache-c.c index a60a24f..0e1e451 100644 --- a/arch/blackfin/mach-common/cache-c.c +++ b/arch/blackfin/mach-common/cache-c.c @@ -52,7 +52,7 @@ bfin_cache_init(struct cplb_entry *cplb_tbl, unsigned long cplb_addr, } #ifdef CONFIG_BFIN_ICACHE -void __cpuinit bfin_icache_init(struct cplb_entry *icplb_tbl) +void bfin_icache_init(struct cplb_entry *icplb_tbl) { bfin_cache_init(icplb_tbl, ICPLB_ADDR0, ICPLB_DATA0, IMEM_CONTROL, (IMC | ENICPLB)); @@ -60,7 +60,7 @@ void __cpuinit bfin_icache_init(struct cplb_entry *icplb_tbl) #endif #ifdef CONFIG_BFIN_DCACHE -void __cpuinit bfin_dcache_init(struct cplb_entry *dcplb_tbl) +void bfin_dcache_init(struct cplb_entry *dcplb_tbl) { /* * Anomaly notes: diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c index 6c0c681..d143fd8 100644 --- a/arch/blackfin/mach-common/ints-priority.c +++ b/arch/blackfin/mach-common/ints-priority.c @@ -1281,7 +1281,7 @@ static struct irq_chip bfin_gpio_irqchip = { .irq_set_wake = bfin_gpio_set_wake, }; -void __cpuinit init_exception_vectors(void) +void init_exception_vectors(void) { /* cannot program in software: * evt0 - emulation (jtag) diff --git a/arch/blackfin/mach-common/scb-init.c b/arch/blackfin/mach-common/scb-init.c new file mode 100644 index 0000000..2cbfb0b --- /dev/null +++ b/arch/blackfin/mach-common/scb-init.c @@ -0,0 +1,53 @@ +/* + * arch/blackfin/mach-common/scb-init.c - reprogram system cross bar priority + * + * Copyright 2012 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include <linux/init.h> +#include <linux/errno.h> +#include <linux/kernel.h> +#include <asm/scb.h> + +__attribute__((l1_text)) +inline void scb_mi_write(unsigned long scb_mi_arbw, unsigned int slots, + unsigned char *scb_mi_prio) +{ + unsigned int i; + + for (i = 0; i < slots; ++i) + bfin_write32(scb_mi_arbw, (i << SCB_SLOT_OFFSET) | scb_mi_prio[i]); +} + +__attribute__((l1_text)) +inline void scb_mi_read(unsigned long scb_mi_arbw, unsigned int slots, + unsigned char *scb_mi_prio) +{ + unsigned int i; + + for (i = 0; i < slots; ++i) { + bfin_write32(scb_mi_arbw, (0xFF << SCB_SLOT_OFFSET) | i); + scb_mi_prio[i] = bfin_read32(scb_mi_arbw); + } +} + +__attribute__((l1_text)) +void init_scb(void) +{ + unsigned int i, j; + unsigned char scb_tmp_prio[32]; + + pr_info("Init System Crossbar\n"); + for (i = 0; scb_data[i].scb_mi_arbr > 0; ++i) { + + scb_mi_write(scb_data[i].scb_mi_arbw, scb_data[i].scb_mi_slots, scb_data[i].scb_mi_prio); + + pr_debug("scb priority at 0x%lx:\n", scb_data[i].scb_mi_arbr); + scb_mi_read(scb_data[i].scb_mi_arbw, scb_data[i].scb_mi_slots, scb_tmp_prio); + for (j = 0; j < scb_data[i].scb_mi_slots; ++j) + pr_debug("slot %d = %d\n", j, scb_tmp_prio[j]); + } + +} diff --git a/arch/blackfin/mach-common/smp.c b/arch/blackfin/mach-common/smp.c index 1bc2ce6..82f301c 100644 --- a/arch/blackfin/mach-common/smp.c +++ b/arch/blackfin/mach-common/smp.c @@ -46,9 +46,10 @@ struct corelock_slot corelock __attribute__ ((__section__(".l2.bss"))); unsigned long blackfin_iflush_l1_entry[NR_CPUS]; #endif -struct blackfin_initial_pda __cpuinitdata initial_pda_coreb; +struct blackfin_initial_pda initial_pda_coreb; enum ipi_message_type { + BFIN_IPI_NONE, BFIN_IPI_TIMER, BFIN_IPI_RESCHEDULE, BFIN_IPI_CALL_FUNC, @@ -72,8 +73,8 @@ static DEFINE_SPINLOCK(stop_lock); /* Simple FIFO buffer, overflow leads to panic */ struct ipi_data { - unsigned long count; - unsigned long bits; + atomic_t count; + atomic_t bits; }; static DEFINE_PER_CPU(struct ipi_data, bfin_ipi); @@ -146,8 +147,7 @@ static irqreturn_t ipi_handler_int1(int irq, void *dev_instance) platform_clear_ipi(cpu, IRQ_SUPPLE_1); bfin_ipi_data = &__get_cpu_var(bfin_ipi); - smp_mb(); - while ((pending = xchg(&bfin_ipi_data->bits, 0)) != 0) { + while ((pending = atomic_xchg(&bfin_ipi_data->bits, 0)) != 0) { msg = 0; do { msg = find_next_bit(&pending, BITS_PER_LONG, msg + 1); @@ -170,9 +170,8 @@ static irqreturn_t ipi_handler_int1(int irq, void *dev_instance) ipi_cpu_stop(cpu); break; } + atomic_dec(&bfin_ipi_data->count); } while (msg < BITS_PER_LONG); - - smp_mb(); } return IRQ_HANDLED; } @@ -183,8 +182,8 @@ static void bfin_ipi_init(void) struct ipi_data *bfin_ipi_data; for_each_possible_cpu(cpu) { bfin_ipi_data = &per_cpu(bfin_ipi, cpu); - bfin_ipi_data->bits = 0; - bfin_ipi_data->count = 0; + atomic_set(&bfin_ipi_data->bits, 0); + atomic_set(&bfin_ipi_data->count, 0); } } @@ -195,12 +194,10 @@ void send_ipi(const struct cpumask *cpumask, enum ipi_message_type msg) unsigned long flags; local_irq_save(flags); - smp_mb(); for_each_cpu(cpu, cpumask) { bfin_ipi_data = &per_cpu(bfin_ipi, cpu); - smp_mb(); - set_bit(msg, &bfin_ipi_data->bits); - bfin_ipi_data->count++; + atomic_set_mask((1 << msg), &bfin_ipi_data->bits); + atomic_inc(&bfin_ipi_data->count); platform_send_ipi_cpu(cpu, IRQ_SUPPLE_1); } @@ -249,7 +246,7 @@ void smp_send_stop(void) return; } -int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle) +int __cpu_up(unsigned int cpu, struct task_struct *idle) { int ret; @@ -262,7 +259,7 @@ int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle) return ret; } -static void __cpuinit setup_secondary(unsigned int cpu) +static void setup_secondary(unsigned int cpu) { unsigned long ilat; @@ -280,7 +277,7 @@ static void __cpuinit setup_secondary(unsigned int cpu) IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW; } -void __cpuinit secondary_start_kernel(void) +void secondary_start_kernel(void) { unsigned int cpu = smp_processor_id(); struct mm_struct *mm = &init_mm; @@ -319,7 +316,6 @@ void __cpuinit secondary_start_kernel(void) setup_secondary(cpu); platform_secondary_init(cpu); - /* setup local core timer */ bfin_local_timer_setup(); @@ -335,6 +331,8 @@ void __cpuinit secondary_start_kernel(void) */ calibrate_delay(); + /* We are done with local CPU inits, unblock the boot CPU. */ + set_cpu_online(cpu, true); cpu_startup_entry(CPUHP_ONLINE); } @@ -404,7 +402,7 @@ EXPORT_SYMBOL(resync_core_dcache); #endif #ifdef CONFIG_HOTPLUG_CPU -int __cpuexit __cpu_disable(void) +int __cpu_disable(void) { unsigned int cpu = smp_processor_id(); @@ -417,7 +415,7 @@ int __cpuexit __cpu_disable(void) static DECLARE_COMPLETION(cpu_killed); -int __cpuexit __cpu_die(unsigned int cpu) +int __cpu_die(unsigned int cpu) { return wait_for_completion_timeout(&cpu_killed, 5000); } diff --git a/arch/blackfin/mm/init.c b/arch/blackfin/mm/init.c index 82d01a7..166842d 100644 --- a/arch/blackfin/mm/init.c +++ b/arch/blackfin/mm/init.c @@ -90,50 +90,24 @@ asmlinkage void __init init_pda(void) void __init mem_init(void) { - unsigned int codek = 0, datak = 0, initk = 0; - unsigned int reservedpages = 0, freepages = 0; - unsigned long tmp; - unsigned long start_mem = memory_start; - unsigned long end_mem = memory_end; + char buf[64]; - end_mem &= PAGE_MASK; - high_memory = (void *)end_mem; - - start_mem = PAGE_ALIGN(start_mem); - max_mapnr = num_physpages = MAP_NR(high_memory); - printk(KERN_DEBUG "Kernel managed physical pages: %lu\n", num_physpages); + high_memory = (void *)(memory_end & PAGE_MASK); + max_mapnr = MAP_NR(high_memory); + printk(KERN_DEBUG "Kernel managed physical pages: %lu\n", max_mapnr); /* This will put all low memory onto the freelists. */ - totalram_pages = free_all_bootmem(); - - reservedpages = 0; - for (tmp = ARCH_PFN_OFFSET; tmp < max_mapnr; tmp++) - if (PageReserved(pfn_to_page(tmp))) - reservedpages++; - freepages = max_mapnr - ARCH_PFN_OFFSET - reservedpages; - - /* do not count in kernel image between _rambase and _ramstart */ - reservedpages -= (_ramstart - _rambase) >> PAGE_SHIFT; -#if (defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) && ANOMALY_05000263) - reservedpages += (_ramend - memory_end - DMA_UNCACHED_REGION) >> PAGE_SHIFT; -#endif - - codek = (_etext - _stext) >> 10; - initk = (__init_end - __init_begin) >> 10; - datak = ((_ramstart - _rambase) >> 10) - codek - initk; + free_all_bootmem(); - printk(KERN_INFO - "Memory available: %luk/%luk RAM, " - "(%uk init code, %uk kernel code, %uk data, %uk dma, %uk reserved)\n", - (unsigned long) freepages << (PAGE_SHIFT-10), (_ramend - CONFIG_PHY_RAM_BASE_ADDRESS) >> 10, - initk, codek, datak, DMA_UNCACHED_REGION >> 10, (reservedpages << (PAGE_SHIFT-10))); + snprintf(buf, sizeof(buf) - 1, "%uK DMA", DMA_UNCACHED_REGION >> 10); + mem_init_print_info(buf); } #ifdef CONFIG_BLK_DEV_INITRD void __init free_initrd_mem(unsigned long start, unsigned long end) { #ifndef CONFIG_MPU - free_reserved_area(start, end, 0, "initrd"); + free_reserved_area((void *)start, (void *)end, -1, "initrd"); #endif } #endif @@ -141,7 +115,7 @@ void __init free_initrd_mem(unsigned long start, unsigned long end) void __init_refok free_initmem(void) { #if defined CONFIG_RAMKERNEL && !defined CONFIG_MPU - free_initmem_default(0); + free_initmem_default(-1); if (memory_start == (unsigned long)(&__init_end)) memory_start = (unsigned long)(&__init_begin); #endif |
