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| author | Mike Frysinger <vapier@gentoo.org> | 2010-05-27 22:46:46 +0000 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2010-08-06 12:55:47 -0400 |
| commit | 74181295fbc6e65047e85529aa74457d82355ffc (patch) | |
| tree | bf218b8d35999e531643d060ac1a8987b71e2259 /arch/blackfin/mach-common | |
| parent | dc7101bbaed644e61aa0056ff572b8d7a58e1ef0 (diff) | |
| download | op-kernel-dev-74181295fbc6e65047e85529aa74457d82355ffc.zip op-kernel-dev-74181295fbc6e65047e85529aa74457d82355ffc.tar.gz | |
Blackfin: allow cache funcs to be in L1 for IFLUSH Anomaly 05000491
Anomaly 05000491 says that IFLUSH cannot have certain types of memory
stalls triggered before it has completed in order to function correctly.
One such condition is that it be in L1 instruction. So add a config
option to move it there, default it to on, and throw up a warning when
it is turned off and this anomaly exists.
Since the anomaly should be worked around, we can drop the older method
of calling IFLUSH multiple times.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Diffstat (limited to 'arch/blackfin/mach-common')
| -rw-r--r-- | arch/blackfin/mach-common/arch_checks.c | 4 | ||||
| -rw-r--r-- | arch/blackfin/mach-common/cache.S | 15 |
2 files changed, 8 insertions, 11 deletions
diff --git a/arch/blackfin/mach-common/arch_checks.c b/arch/blackfin/mach-common/arch_checks.c index 77d1c32..bceb981 100644 --- a/arch/blackfin/mach-common/arch_checks.c +++ b/arch/blackfin/mach-common/arch_checks.c @@ -60,3 +60,7 @@ (defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)) # error "Anomaly 05000220 does not allow you to use Write Back cache with L2 or External Memory" #endif + +#if ANOMALY_05000491 && !defined(CONFIG_CACHE_FLUSH_L1) +# error You need IFLUSH in L1 inst while Anomaly 05000491 applies +#endif diff --git a/arch/blackfin/mach-common/cache.S b/arch/blackfin/mach-common/cache.S index ea54031..790c767 100644 --- a/arch/blackfin/mach-common/cache.S +++ b/arch/blackfin/mach-common/cache.S @@ -11,7 +11,11 @@ #include <asm/cache.h> #include <asm/page.h> +#ifdef CONFIG_CACHE_FLUSH_L1 +.section .l1.text +#else .text +#endif /* 05000443 - IFLUSH cannot be last instruction in hardware loop */ #if ANOMALY_05000443 @@ -64,17 +68,6 @@ /* Invalidate all instruction cache lines assocoiated with this memory area */ ENTRY(_blackfin_icache_flush_range) -/* - * Walkaround to avoid loading wrong instruction after invalidating icache - * and following sequence is met. - * - * 1) One instruction address is cached in the instruction cache. - * 2) This instruction in SDRAM is changed. - * 3) IFLASH[P0] is executed only once in blackfin_icache_flush_range(). - * 4) This instruction is executed again, but the old one is loaded. - */ - P0 = R0; - IFLUSH[P0]; do_flush IFLUSH ENDPROC(_blackfin_icache_flush_range) |
