Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin: (32 commits)
  Blackfin: gpio: add a debounce stub
  Blackfin: update defconfigs
  Blackfin: remove CONFIG_MEM_GENERIC_BOARD
  Blackfin: dpmc: punt unnecessary RTC_ISTAT clearing
  Blackfin: unify rotary encoder bitmasks
  Blackfin: unify SDH/RSI bitmasks
  Blackfin: BF54x: tweak DMAC MMR naming to match other ports
  Blackfin: TWI: clean up the MMR names
  Blackfin: add EVT_OVERRIDE/IPRIO core MMR helpers
  Blackfin: add support for dynamic ftrace
  Blackfin: add support for LZO compressed kernels
  Blackfin: portmux: fix peripheral map overflow when requesting pins
  Blackfin: document SPI CS limitations with CPHA=0
  Blackfin: remove useless and outdated documentation
  Blackfin: BF51x/BF52x: support GPIO Hysteresis/Schmitt Trigger options
  Blackfin: gpio/portmux: clean up whitespace corruption
  Blackfin: make sure mmiowb inserts a write barrier with SSYNC
  Blackfin: fix DMA/cache bug when resuming from suspend to RAM
  Blackfin: BF51x: fix handling of PH8 (the "internal" SPI0SEL4 pin)
  Blackfin: add a GPIO_DEFAULT_BOOT_SPI_CS
  ...

1 files changed, 17 insertions, 4 deletions

diff --git a/arch/blackfin/mach-bf518/include/mach/anomaly.h b/arch/blackfin/mach-bf518/include/mach/anomaly.h
index 2829dd0..24918c5 100644
--- a/arch/blackfin/mach-bf518/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf518/include/mach/anomaly.h
@@ -5,13 +5,13 @@
  * and can be replaced with that version at any time
  * DO NOT EDIT THIS FILE
  *
- * Copyright 2004-2009 Analog Devices Inc.
+ * Copyright 2004-2010 Analog Devices Inc.
  * Licensed under the ADI BSD license.
  *   https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
  */
 
 /* This file should be up to date with:
- *  - Revision C, 06/12/2009; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List
+ *  - Revision E, 01/26/2010; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List
  */
 
 /* We plan on not supporting 0.0 silicon, but 0.1 isn't out yet - sorry */
@@ -24,6 +24,8 @@
 
 /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
 #define ANOMALY_05000074 (1)
+/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
+#define ANOMALY_05000119 (1)
 /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
 #define ANOMALY_05000122 (1)
 /* False Hardware Error from an Access in the Shadow of a Conditional Branch */
@@ -52,6 +54,8 @@
 #define ANOMALY_05000430 (__SILICON_REVISION__ < 1)
 /* Incorrect Use of Stack in Lockbox Firmware During Authentication */
 #define ANOMALY_05000431 (1)
+/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
+#define ANOMALY_05000434 (1)
 /* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */
 #define ANOMALY_05000435 (__SILICON_REVISION__ < 1)
 /* PORTx_DRIVE and PORTx_HYSTERESIS Registers Read Back Incorrect Values */
@@ -74,14 +78,21 @@
 #define ANOMALY_05000461 (1)
 /* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
 #define ANOMALY_05000462 (1)
-/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
+/* PLL Latches Incorrect Settings During Reset */
+#define ANOMALY_05000469 (1)
+/* Incorrect Default MSEL Value in PLL_CTL */
+#define ANOMALY_05000472 (1)
+/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
 #define ANOMALY_05000473 (1)
 /* TESTSET Instruction Cannot Be Interrupted */
 #define ANOMALY_05000477 (1)
+/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
+#define ANOMALY_05000481 (1)
+/* IFLUSH sucks at life */
+#define ANOMALY_05000491 (1)
 
 /* Anomalies that don't exist on this proc */
 #define ANOMALY_05000099 (0)
-#define ANOMALY_05000119 (0)
 #define ANOMALY_05000120 (0)
 #define ANOMALY_05000125 (0)
 #define ANOMALY_05000149 (0)
@@ -94,6 +105,7 @@
 #define ANOMALY_05000198 (0)
 #define ANOMALY_05000202 (0)
 #define ANOMALY_05000215 (0)
+#define ANOMALY_05000219 (0)
 #define ANOMALY_05000220 (0)
 #define ANOMALY_05000227 (0)
 #define ANOMALY_05000230 (0)
@@ -143,5 +155,6 @@
 #define ANOMALY_05000467 (0)
 #define ANOMALY_05000474 (0)
 #define ANOMALY_05000475 (0)
+#define ANOMALY_05000485 (0)
 
 #endif