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authorBernd Schmidt <bernds_cb1@t-online.de>2009-09-02 08:14:05 +0000
committerMike Frysinger <vapier@gentoo.org>2009-09-16 22:10:42 -0400
commit4663f6ef251766cc9f7ab21af35661d8a736bef2 (patch)
tree070e479dd1ecb89a57a3aa12884d67a43573f407 /arch/blackfin/kernel
parent4a3e53c1c4dd44b9d0fa1537c1294eb72229bfce (diff)
downloadop-kernel-dev-4663f6ef251766cc9f7ab21af35661d8a736bef2.zip
op-kernel-dev-4663f6ef251766cc9f7ab21af35661d8a736bef2.tar.gz
Blackfin: add ICPLB coverage for async banks
When doing XIP, we need to execute out of the async banks, so we need ICPLBs to allow this. Signed-off-by: Bernd Schmidt <bernds_cb1@t-online.de> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/kernel')
-rw-r--r--arch/blackfin/kernel/cplb-nompu/cplbinit.c11
1 files changed, 9 insertions, 2 deletions
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinit.c b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
index 685f160..5d8ad503 100644
--- a/arch/blackfin/kernel/cplb-nompu/cplbinit.c
+++ b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
@@ -36,7 +36,7 @@ int first_switched_icplb PDT_ATTR;
int first_switched_dcplb PDT_ATTR;
struct cplb_boundary dcplb_bounds[9] PDT_ATTR;
-struct cplb_boundary icplb_bounds[7] PDT_ATTR;
+struct cplb_boundary icplb_bounds[9] PDT_ATTR;
int icplb_nr_bounds PDT_ATTR;
int dcplb_nr_bounds PDT_ATTR;
@@ -167,14 +167,21 @@ void __init generate_cplb_tables_all(void)
icplb_bounds[i_i++].data = (reserved_mem_icache_on ?
SDRAM_IGENERIC : SDRAM_INON_CHBL);
}
+ /* Addressing hole up to the async bank. */
+ icplb_bounds[i_i].eaddr = ASYNC_BANK0_BASE;
+ icplb_bounds[i_i++].data = 0;
+ /* ASYNC banks. */
+ icplb_bounds[i_i].eaddr = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE;
+ icplb_bounds[i_i++].data = SDRAM_EBIU;
/* Addressing hole up to BootROM. */
icplb_bounds[i_i].eaddr = BOOT_ROM_START;
icplb_bounds[i_i++].data = 0;
/* BootROM -- largest one should be less than 1 meg. */
icplb_bounds[i_i].eaddr = BOOT_ROM_START + (1 * 1024 * 1024);
icplb_bounds[i_i++].data = SDRAM_IGENERIC;
+
if (L2_LENGTH) {
- /* Addressing hole up to L2 SRAM, including the async bank. */
+ /* Addressing hole up to L2 SRAM. */
icplb_bounds[i_i].eaddr = L2_START;
icplb_bounds[i_i++].data = 0;
/* L2 SRAM. */
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