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| author | Russell King <rmk+kernel@arm.linux.org.uk> | 2009-09-22 20:54:53 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2009-09-22 21:01:40 +0100 |
| commit | ae19ffbadc1b2100285a5b5b3d0a4e0a11390904 (patch) | |
| tree | 3c2086ab67398a019089a47ca3f362a4bc6db74f /arch/blackfin/kernel/cplb-nompu/cplbinit.c | |
| parent | 34e84f39a27d059a3e6ec6e8b94aafa702e6f220 (diff) | |
| parent | 9173a8ef24a6b1b8031507b35b8ffe5f85a87692 (diff) | |
| download | op-kernel-dev-ae19ffbadc1b2100285a5b5b3d0a4e0a11390904.zip op-kernel-dev-ae19ffbadc1b2100285a5b5b3d0a4e0a11390904.tar.gz | |
Merge branch 'master' into for-linus
Diffstat (limited to 'arch/blackfin/kernel/cplb-nompu/cplbinit.c')
| -rw-r--r-- | arch/blackfin/kernel/cplb-nompu/cplbinit.c | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinit.c b/arch/blackfin/kernel/cplb-nompu/cplbinit.c index 685f160..5d8ad503 100644 --- a/arch/blackfin/kernel/cplb-nompu/cplbinit.c +++ b/arch/blackfin/kernel/cplb-nompu/cplbinit.c @@ -36,7 +36,7 @@ int first_switched_icplb PDT_ATTR; int first_switched_dcplb PDT_ATTR; struct cplb_boundary dcplb_bounds[9] PDT_ATTR; -struct cplb_boundary icplb_bounds[7] PDT_ATTR; +struct cplb_boundary icplb_bounds[9] PDT_ATTR; int icplb_nr_bounds PDT_ATTR; int dcplb_nr_bounds PDT_ATTR; @@ -167,14 +167,21 @@ void __init generate_cplb_tables_all(void) icplb_bounds[i_i++].data = (reserved_mem_icache_on ? SDRAM_IGENERIC : SDRAM_INON_CHBL); } + /* Addressing hole up to the async bank. */ + icplb_bounds[i_i].eaddr = ASYNC_BANK0_BASE; + icplb_bounds[i_i++].data = 0; + /* ASYNC banks. */ + icplb_bounds[i_i].eaddr = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE; + icplb_bounds[i_i++].data = SDRAM_EBIU; /* Addressing hole up to BootROM. */ icplb_bounds[i_i].eaddr = BOOT_ROM_START; icplb_bounds[i_i++].data = 0; /* BootROM -- largest one should be less than 1 meg. */ icplb_bounds[i_i].eaddr = BOOT_ROM_START + (1 * 1024 * 1024); icplb_bounds[i_i++].data = SDRAM_IGENERIC; + if (L2_LENGTH) { - /* Addressing hole up to L2 SRAM, including the async bank. */ + /* Addressing hole up to L2 SRAM. */ icplb_bounds[i_i].eaddr = L2_START; icplb_bounds[i_i++].data = 0; /* L2 SRAM. */ |
