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authorLinus Torvalds <torvalds@linux-foundation.org>2008-01-28 08:15:24 +1100
committerLinus Torvalds <torvalds@linux-foundation.org>2008-01-28 08:15:24 +1100
commit91525300baf162e83e923b09ca286f9205e21522 (patch)
tree115f50c0f270eb1bb032dc520e018d9aa65b957c /arch/blackfin/kernel/cplb-mpu/cacheinit.c
parent991dee591a99d035796a8c194eb1796cc020e142 (diff)
parent9c5e710bc1431f41ccdd0c294fa355aa0d45d2d7 (diff)
downloadop-kernel-dev-91525300baf162e83e923b09ca286f9205e21522.zip
op-kernel-dev-91525300baf162e83e923b09ca286f9205e21522.tar.gz
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/blackfin-2.6
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/blackfin-2.6: (54 commits) MAINTIANERS: just use Mike gmail e-mail for contact and pawn the serial driver off onto Sonic [Blackfin] arch: remove old I2C BF54x porting. [Blackfin] arch: Add the semtimedop syscall. Upstream uClibc doesn't compile without it. [Blackfin] arch: fix bug kernel boot message: memory information is not reasonable [Blackfin] arch: use common flash driver to setup partitions rather than the bf5xx-flash driver [Blackfin] arch: Fix bug - kernel build with Debug option enabled fails to boot up [Blackfin] arch: Fix bug Only RTC interrupt can wake up deeper sleep core. [Blackfin] arch: Add proper SW System Reset delay sequence [Blackfin] arch: Update copyright date [Blackfin] arch: GPIO API cleanup and anomaly update [Blackfin] arch: Fix BUG gpio_direction_output API is not compatitable with GENERIC_GPIO API interface [Blackfin] arch: Initial checkin of the memory protection support. [Blackfin] arch: set_bfin_dma_config shouldnt set SYNC or RESTART by default - add argument or option [Blackfin] arch: Add some comments - fix semicolons [Blackfin] arch: move all code related to CPLB handling into a new subdirectory under kernel/ [Blackfin] arch: print out list of modules if kernel is crashing and tell people if the kernel is tainted [Blackfin] arch: enable generic GPIO based I2C driver in STAMP-BF533, EZKIT-BF533 and EZKIT-BF561 boards [Blackfin] arch: Don't oops_in_progress if single step is comming from the kernel [Blackfin] arch: Fix BUG - kernel sometimes would stuck with KEYBOARD_GPIO on [Blackfin] arch: update to latest anomaly sheets ...
Diffstat (limited to 'arch/blackfin/kernel/cplb-mpu/cacheinit.c')
-rw-r--r--arch/blackfin/kernel/cplb-mpu/cacheinit.c62
1 files changed, 62 insertions, 0 deletions
diff --git a/arch/blackfin/kernel/cplb-mpu/cacheinit.c b/arch/blackfin/kernel/cplb-mpu/cacheinit.c
new file mode 100644
index 0000000..9eecfa4
--- /dev/null
+++ b/arch/blackfin/kernel/cplb-mpu/cacheinit.c
@@ -0,0 +1,62 @@
+/*
+ * Copyright 2004-2007 Analog Devices Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <linux/cpu.h>
+
+#include <asm/cacheflush.h>
+#include <asm/blackfin.h>
+#include <asm/cplb.h>
+#include <asm/cplbinit.h>
+
+#if defined(CONFIG_BFIN_ICACHE)
+void bfin_icache_init(void)
+{
+ unsigned long ctrl;
+ int i;
+
+ SSYNC();
+ for (i = 0; i < MAX_CPLBS; i++) {
+ bfin_write32(ICPLB_ADDR0 + i * 4, icplb_tbl[i].addr);
+ bfin_write32(ICPLB_DATA0 + i * 4, icplb_tbl[i].data);
+ }
+ ctrl = bfin_read_IMEM_CONTROL();
+ ctrl |= IMC | ENICPLB;
+ bfin_write_IMEM_CONTROL(ctrl);
+ SSYNC();
+}
+#endif
+
+#if defined(CONFIG_BFIN_DCACHE)
+void bfin_dcache_init(void)
+{
+ unsigned long ctrl;
+ int i;
+
+ SSYNC();
+ for (i = 0; i < MAX_CPLBS; i++) {
+ bfin_write32(DCPLB_ADDR0 + i * 4, dcplb_tbl[i].addr);
+ bfin_write32(DCPLB_DATA0 + i * 4, dcplb_tbl[i].data);
+ }
+
+ ctrl = bfin_read_DMEM_CONTROL();
+ ctrl |= DMEM_CNTR;
+ bfin_write_DMEM_CONTROL(ctrl);
+ SSYNC();
+}
+#endif
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