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author | Ingo Molnar <mingo@elte.hu> | 2011-05-26 13:51:31 +0200 |
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committer | Ingo Molnar <mingo@elte.hu> | 2011-05-26 13:51:35 +0200 |
commit | de66ee979d0ea45171cc2501750e9f9f22f5a690 (patch) | |
tree | 5ab1a5c6b596b9b786902fb380274e1e1f4ceb13 /arch/blackfin/include/mach-common/irq.h | |
parent | 916f676f8dc016103f983c7ec54c18ecdbb6e349 (diff) | |
parent | 4db70f73e56961b9bcdfd0c36c62847a18b7dbb5 (diff) | |
download | op-kernel-dev-de66ee979d0ea45171cc2501750e9f9f22f5a690.zip op-kernel-dev-de66ee979d0ea45171cc2501750e9f9f22f5a690.tar.gz |
Merge branch 'linus' into x86/urgent
Merge reason: we want to queue up a dependent patch.
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/blackfin/include/mach-common/irq.h')
-rw-r--r-- | arch/blackfin/include/mach-common/irq.h | 57 |
1 files changed, 57 insertions, 0 deletions
diff --git a/arch/blackfin/include/mach-common/irq.h b/arch/blackfin/include/mach-common/irq.h new file mode 100644 index 0000000..cab14e9 --- /dev/null +++ b/arch/blackfin/include/mach-common/irq.h @@ -0,0 +1,57 @@ +/* + * Common Blackfin IRQ definitions (i.e. the CEC) + * + * Copyright 2005-2011 Analog Devices Inc. + * + * Licensed under the GPL-2 or later + */ + +#ifndef _MACH_COMMON_IRQ_H_ +#define _MACH_COMMON_IRQ_H_ + +/* + * Core events interrupt source definitions + * + * Event Source Event Name + * Emulation EMU 0 (highest priority) + * Reset RST 1 + * NMI NMI 2 + * Exception EVX 3 + * Reserved -- 4 + * Hardware Error IVHW 5 + * Core Timer IVTMR 6 + * Peripherals IVG7 7 + * Peripherals IVG8 8 + * Peripherals IVG9 9 + * Peripherals IVG10 10 + * Peripherals IVG11 11 + * Peripherals IVG12 12 + * Peripherals IVG13 13 + * Softirq IVG14 14 + * System Call IVG15 15 (lowest priority) + */ + +/* The ABSTRACT IRQ definitions */ +#define IRQ_EMU 0 /* Emulation */ +#define IRQ_RST 1 /* reset */ +#define IRQ_NMI 2 /* Non Maskable */ +#define IRQ_EVX 3 /* Exception */ +#define IRQ_UNUSED 4 /* - unused interrupt */ +#define IRQ_HWERR 5 /* Hardware Error */ +#define IRQ_CORETMR 6 /* Core timer */ + +#define BFIN_IRQ(x) ((x) + 7) + +#define IVG7 7 +#define IVG8 8 +#define IVG9 9 +#define IVG10 10 +#define IVG11 11 +#define IVG12 12 +#define IVG13 13 +#define IVG14 14 +#define IVG15 15 + +#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS) + +#endif |