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authorCatalin Marinas <catalin.marinas@arm.com>2014-04-22 16:14:27 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2014-04-25 12:06:37 +0100
commit431a84b1a4f7d1a0085d5b91330c5053cc8e8b12 (patch)
treec4291aef9feb162eefe9cad19b290231f0c4d6f9 /arch/arm
parenta05e54c103b0b8e1dab5d04b411f1d48387c4903 (diff)
downloadop-kernel-dev-431a84b1a4f7d1a0085d5b91330c5053cc8e8b12.zip
op-kernel-dev-431a84b1a4f7d1a0085d5b91330c5053cc8e8b12.tar.gz
ARM: 8034/1: Disable preemption in iwmmxt_task_enable()
This patch is in preparation for calling the iwmmxt_task_enable() function with interrupts enabled. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/kernel/iwmmxt.S14
1 files changed, 11 insertions, 3 deletions
diff --git a/arch/arm/kernel/iwmmxt.S b/arch/arm/kernel/iwmmxt.S
index a087838..fcb33a7 100644
--- a/arch/arm/kernel/iwmmxt.S
+++ b/arch/arm/kernel/iwmmxt.S
@@ -18,6 +18,7 @@
#include <asm/ptrace.h>
#include <asm/thread_info.h>
#include <asm/asm-offsets.h>
+#include <asm/assembler.h>
#if defined(CONFIG_CPU_PJ4)
#define PJ4(code...) code
@@ -65,13 +66,14 @@
*/
ENTRY(iwmmxt_task_enable)
+ inc_preempt_count r10, r3
XSC(mrc p15, 0, r2, c15, c1, 0)
PJ4(mrc p15, 0, r2, c1, c0, 2)
@ CP0 and CP1 accessible?
XSC(tst r2, #0x3)
PJ4(tst r2, #0xf)
- movne pc, lr @ if so no business here
+ bne 4f @ if so no business here
@ enable access to CP0 and CP1
XSC(orr r2, r2, #0x3)
XSC(mcr p15, 0, r2, c15, c1, 0)
@@ -132,7 +134,7 @@ concan_dump:
wstrd wR15, [r1, #MMX_WR15]
2: teq r0, #0 @ anything to load?
- moveq pc, lr
+ beq 3f
concan_load:
@@ -165,8 +167,14 @@ concan_load:
@ clear CUP/MUP (only if r1 != 0)
teq r1, #0
mov r2, #0
- moveq pc, lr
+ beq 3f
tmcr wCon, r2
+
+3:
+#ifdef CONFIG_PREEMPT_COUNT
+ get_thread_info r10
+#endif
+4: dec_preempt_count r10, r3
mov pc, lr
/*
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