diff options
author | Shawn Guo <shawn.guo@linaro.org> | 2013-07-23 15:56:29 +0800 |
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committer | Shawn Guo <shawn.guo@linaro.org> | 2013-08-22 23:29:46 +0800 |
commit | ea257a0328c201cc29dd49d01d3682f106c1249e (patch) | |
tree | c187055ab68d7426ea3d75f6c5d2f053ea9e4b11 /arch/arm | |
parent | 951ebf58bf2a668c385df4ce8f2f3285afa0763c (diff) | |
download | op-kernel-dev-ea257a0328c201cc29dd49d01d3682f106c1249e.zip op-kernel-dev-ea257a0328c201cc29dd49d01d3682f106c1249e.tar.gz |
ARM: imx: add ocram clock for imx53
Add missing ocram gate clock for imx53 and also represent it in device
tree ocram node.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/boot/dts/imx53.dtsi | 1 | ||||
-rw-r--r-- | arch/arm/mach-imx/clk-imx51-imx53.c | 3 |
2 files changed, 3 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 44a0170..4307e80 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -1121,6 +1121,7 @@ ocram: sram@f8000000 { compatible = "mmio-sram"; reg = <0xf8000000 0x20000>; + clocks = <&clks 186>; }; }; }; diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c index 9afac26..1a56a33 100644 --- a/arch/arm/mach-imx/clk-imx51-imx53.c +++ b/arch/arm/mach-imx/clk-imx51-imx53.c @@ -119,7 +119,7 @@ enum imx5_clks { srtc_gate, pata_gate, sata_gate, spdif_xtal_sel, spdif0_sel, spdif1_sel, spdif0_pred, spdif0_podf, spdif1_pred, spdif1_podf, spdif0_com_s, spdif1_com_sel, spdif0_gate, spdif1_gate, spdif_ipg_gate, - clk_max + ocram, clk_max }; static struct clk *clk[clk_max]; @@ -506,6 +506,7 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc, mx53_can_sel, ARRAY_SIZE(mx53_can_sel)); clk[can1_serial_gate] = imx_clk_gate2("can1_serial_gate", "can_sel", MXC_CCM_CCGR6, 22); clk[can1_ipg_gate] = imx_clk_gate2("can1_ipg_gate", "ipg", MXC_CCM_CCGR6, 20); + clk[ocram] = imx_clk_gate2("ocram", "ahb", MXC_CCM_CCGR6, 2); clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8); clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6); clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22); |