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| author | Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> | 2013-03-27 00:55:24 -0700 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2013-04-02 11:02:15 +0900 |
| commit | b3186c68805911599cbacceae23f60debb5e2210 (patch) | |
| tree | 5671f3780754dc84006d7f6e7b6f9d7bc12a91d7 /arch/arm | |
| parent | 1f7ccd88717d993c5189280034f1d3b6b5af9693 (diff) | |
| download | op-kernel-dev-b3186c68805911599cbacceae23f60debb5e2210.zip op-kernel-dev-b3186c68805911599cbacceae23f60debb5e2210.tar.gz | |
ARM: shmobile: sh7372: remove DIV4_ZT* clocks
DIV4_ZT* clocks are for debugging and trace bus clock.
It is not necessary to control it from Linux/Software.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/mach-shmobile/clock-sh7372.c | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c index 45d21fe..6c23e3f 100644 --- a/arch/arm/mach-shmobile/clock-sh7372.c +++ b/arch/arm/mach-shmobile/clock-sh7372.c @@ -342,7 +342,7 @@ static struct clk_div4_table div4_table = { }; enum { DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_CSIR, - DIV4_ZTR, DIV4_ZT, DIV4_ZX, DIV4_HP, + DIV4_ZX, DIV4_HP, DIV4_ISPB, DIV4_S, DIV4_ZB, DIV4_ZB3, DIV4_CP, DIV4_DDRP, DIV4_NR }; @@ -355,8 +355,6 @@ static struct clk div4_clks[DIV4_NR] = { [DIV4_B] = DIV4(FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT), [DIV4_M1] = DIV4(FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT), [DIV4_CSIR] = DIV4(FRQCRA, 0, 0x6fff, 0), - [DIV4_ZTR] = DIV4(FRQCRB, 20, 0x6fff, 0), - [DIV4_ZT] = DIV4(FRQCRB, 16, 0x6fff, 0), [DIV4_ZX] = DIV4(FRQCRB, 12, 0x6fff, 0), [DIV4_HP] = DIV4(FRQCRB, 4, 0x6fff, 0), [DIV4_ISPB] = DIV4(FRQCRC, 20, 0x6fff, 0), @@ -516,8 +514,6 @@ static struct clk_lookup lookups[] = { CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]), CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]), CLKDEV_CON_ID("csir_clk", &div4_clks[DIV4_CSIR]), - CLKDEV_CON_ID("ztr_clk", &div4_clks[DIV4_ZTR]), - CLKDEV_CON_ID("zt_clk", &div4_clks[DIV4_ZT]), CLKDEV_CON_ID("zx_clk", &div4_clks[DIV4_ZX]), CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]), CLKDEV_CON_ID("ispb_clk", &div4_clks[DIV4_ISPB]), |
