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author | Olof Johansson <olof@lixom.net> | 2013-08-29 14:07:34 -0700 |
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committer | Olof Johansson <olof@lixom.net> | 2013-08-29 14:07:34 -0700 |
commit | 6f244c9ccf22bc38d2ce39b1c7ee304dab7e5328 (patch) | |
tree | 633d36d251f645c23feb0dc981f2e0ab7ab7e7bb /arch/arm | |
parent | ef2fd3b15bd2da46e13cc61d475286e5e6026211 (diff) | |
parent | 746831d5a166b1965034318ab80a7a7af03bf30f (diff) | |
download | op-kernel-dev-6f244c9ccf22bc38d2ce39b1c7ee304dab7e5328.zip op-kernel-dev-6f244c9ccf22bc38d2ce39b1c7ee304dab7e5328.tar.gz |
Merge tag 'at91-soc' of git://github.com/at91linux/linux-at91 into late/all
From Nicolas Ferre:
AT91 SoC update for 3.12 take 1
- enable kernel uncompress information output for
SoC where it was missing: at91sam9n12 and sama5d3
- addition of at91rm9200 to the generic at91_dt_defconfig
* tag 'at91-soc' of git://github.com/at91linux/linux-at91:
ARM: at91: at91_dt_defconfig: enable rm9200 support
ARM: at91: sam9n12: enable kernel uncompress info output
ARM: at91: sama5: enable kernel uncompress info output
ARM: at91: include sama5d3.h into hardware.h
ARM: at91: sama5d3: add definition for usart base address
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/configs/at91_dt_defconfig | 4 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/hardware.h | 1 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/sama5d3.h | 8 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/uncompress.h | 13 |
4 files changed, 25 insertions, 1 deletions
diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig index 75fd842..690e892 100644 --- a/arch/arm/configs/at91_dt_defconfig +++ b/arch/arm/configs/at91_dt_defconfig @@ -14,11 +14,13 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_IOSCHED_DEADLINE is not set # CONFIG_IOSCHED_CFQ is not set CONFIG_ARCH_AT91=y +CONFIG_SOC_AT91RM9200=y CONFIG_SOC_AT91SAM9260=y CONFIG_SOC_AT91SAM9263=y CONFIG_SOC_AT91SAM9G45=y CONFIG_SOC_AT91SAM9X5=y CONFIG_SOC_AT91SAM9N12=y +CONFIG_MACH_AT91RM9200_DT=y CONFIG_MACH_AT91SAM9_DT=y CONFIG_AT91_PROGRAMMABLE_CLOCKS=y CONFIG_AT91_TIMER_HZ=128 @@ -62,6 +64,7 @@ CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y +CONFIG_MTD_DATAFLASH=y CONFIG_MTD_NAND=y CONFIG_MTD_NAND_ATMEL=y CONFIG_MTD_UBI=y @@ -78,7 +81,6 @@ CONFIG_BLK_DEV_SD=y CONFIG_SCSI_MULTI_LUN=y # CONFIG_SCSI_LOWLEVEL is not set CONFIG_NETDEVICES=y -CONFIG_MII=y CONFIG_MACB=y # CONFIG_NET_VENDOR_BROADCOM is not set # CONFIG_NET_VENDOR_FARADAY is not set diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h index a832e07..f17aa31 100644 --- a/arch/arm/mach-at91/include/mach/hardware.h +++ b/arch/arm/mach-at91/include/mach/hardware.h @@ -33,6 +33,7 @@ #include <mach/at91sam9g45.h> #include <mach/at91sam9x5.h> #include <mach/at91sam9n12.h> +#include <mach/sama5d3.h> /* * On all at91 except rm9200 and x40 have the System Controller starts diff --git a/arch/arm/mach-at91/include/mach/sama5d3.h b/arch/arm/mach-at91/include/mach/sama5d3.h index 6dc81ee..31096a8 100644 --- a/arch/arm/mach-at91/include/mach/sama5d3.h +++ b/arch/arm/mach-at91/include/mach/sama5d3.h @@ -65,6 +65,14 @@ #define SAMA5D3_ID_IRQ0 47 /* Advanced Interrupt Controller (IRQ0) */ /* + * User Peripheral physical base addresses. + */ +#define SAMA5D3_BASE_USART0 0xf001c000 +#define SAMA5D3_BASE_USART1 0xf0020000 +#define SAMA5D3_BASE_USART2 0xf8020000 +#define SAMA5D3_BASE_USART3 0xf8024000 + +/* * Internal Memory */ #define SAMA5D3_SRAM_BASE 0x00300000 /* Internal SRAM base address */ diff --git a/arch/arm/mach-at91/include/mach/uncompress.h b/arch/arm/mach-at91/include/mach/uncompress.h index 5659f7c..4bb644f 100644 --- a/arch/arm/mach-at91/include/mach/uncompress.h +++ b/arch/arm/mach-at91/include/mach/uncompress.h @@ -94,6 +94,15 @@ static const u32 uarts_sam9x5[] = { 0, }; +static const u32 uarts_sama5[] = { + AT91_BASE_DBGU1, + SAMA5D3_BASE_USART0, + SAMA5D3_BASE_USART1, + SAMA5D3_BASE_USART2, + SAMA5D3_BASE_USART3, + 0, +}; + static inline const u32* decomp_soc_detect(void __iomem *dbgu_base) { u32 cidr, socid; @@ -121,8 +130,12 @@ static inline const u32* decomp_soc_detect(void __iomem *dbgu_base) case ARCH_ID_AT91SAM9RL64: return uarts_sam9rl; + case ARCH_ID_AT91SAM9N12: case ARCH_ID_AT91SAM9X5: return uarts_sam9x5; + + case ARCH_ID_SAMA5D3: + return uarts_sama5; } /* at91sam9g10 */ |