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authorKevin Hilman <khilman@deeprootsystems.com>2009-06-04 15:57:10 -0700
committerKevin Hilman <khilman@deeprootsystems.com>2009-08-05 09:10:54 -0700
commit55b6019ae29456e0f1e4087546bf4221c48622a0 (patch)
tree73a996485891daa8fa0fbb9b55f1f62bc5d5279a /arch/arm
parent6c5f80393b107b0c9e2a54b03b65d1880e706655 (diff)
downloadop-kernel-dev-55b6019ae29456e0f1e4087546bf4221c48622a0.zip
op-kernel-dev-55b6019ae29456e0f1e4087546bf4221c48622a0.tar.gz
OMAP: GPIO: clear/restore level/edge detect settings on mask/unmask
If IRQ triggering is enabled, it can trigger a pending interrupt even for masked interrupts. Any pending GPIO interrupts can prevent the powerdomain from hitting retention. Problem found, reported and additional review and testing by Chunquiu Wang. Tested-by: Chunquiu Wang <cqwang@motorola.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/plat-omap/gpio.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 26b387c..77bad14 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -1189,6 +1189,7 @@ static void gpio_mask_irq(unsigned int irq)
struct gpio_bank *bank = get_irq_chip_data(irq);
_set_gpio_irqenable(bank, gpio, 0);
+ _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
}
static void gpio_unmask_irq(unsigned int irq)
@@ -1196,6 +1197,11 @@ static void gpio_unmask_irq(unsigned int irq)
unsigned int gpio = irq - IH_GPIO_BASE;
struct gpio_bank *bank = get_irq_chip_data(irq);
unsigned int irq_mask = 1 << get_gpio_index(gpio);
+ struct irq_desc *desc = irq_to_desc(irq);
+ u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK;
+
+ if (trigger)
+ _set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
/* For level-triggered GPIOs, the clearing must be done after
* the HW source is cleared, thus after the handler has run */
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