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authorArchit Taneja <archit@ti.com>2011-10-07 03:08:44 -0600
committerPaul Walmsley <paul@pwsan.com>2011-10-07 03:08:44 -0600
commit46f8c3c7e95c0d30d95911e7975ddc4f93b3e237 (patch)
tree39ac4917cc937ccf11986b2988984e43ff6e1836 /arch/arm
parentbe73246058737beec52ae232bcab7776332a9e06 (diff)
downloadop-kernel-dev-46f8c3c7e95c0d30d95911e7975ddc4f93b3e237.zip
op-kernel-dev-46f8c3c7e95c0d30d95911e7975ddc4f93b3e237.tar.gz
ARM: OMAP: ctrl: Fix CONTROL_DSIPHY register fields
Fix the shift and mask macros for DSIx_PPID fields in CONTROL_DSIPHY. The OMAP4430 Public TRM vV has these fields mentioned correctly. Signed-off-by: Archit Taneja <archit@ti.com> Acked-by: Benoit Cousson <b-cousson@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h8
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h
index c88420d..1e2d332 100644
--- a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h
+++ b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h
@@ -941,10 +941,10 @@
#define OMAP4_DSI2_LANEENABLE_MASK (0x7 << 29)
#define OMAP4_DSI1_LANEENABLE_SHIFT 24
#define OMAP4_DSI1_LANEENABLE_MASK (0x1f << 24)
-#define OMAP4_DSI1_PIPD_SHIFT 19
-#define OMAP4_DSI1_PIPD_MASK (0x1f << 19)
-#define OMAP4_DSI2_PIPD_SHIFT 14
-#define OMAP4_DSI2_PIPD_MASK (0x1f << 14)
+#define OMAP4_DSI2_PIPD_SHIFT 19
+#define OMAP4_DSI2_PIPD_MASK (0x1f << 19)
+#define OMAP4_DSI1_PIPD_SHIFT 14
+#define OMAP4_DSI1_PIPD_MASK (0x1f << 14)
/* CONTROL_MCBSPLP */
#define OMAP4_ALBCTRLRX_FSX_SHIFT 31
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