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| author | Marc Zyngier <marc.zyngier@arm.com> | 2015-03-10 19:07:01 +0000 |
|---|---|---|
| committer | Christoffer Dall <christoffer.dall@linaro.org> | 2015-03-11 14:24:37 +0100 |
| commit | 84ed7412b5eee1011579b3db7454b9cb6d26fa65 (patch) | |
| tree | e39b89c02fbf638315126b4684ada6cf75b9da71 /arch/arm64 | |
| parent | 04b8dc85bf4a64517e3cf20e409eeaa503b15cc1 (diff) | |
| download | op-kernel-dev-84ed7412b5eee1011579b3db7454b9cb6d26fa65.zip op-kernel-dev-84ed7412b5eee1011579b3db7454b9cb6d26fa65.tar.gz | |
arm64: KVM: Fix outdated comment about VTCR_EL2.PS
Commit 87366d8cf7b3 ("arm64: Add boot time configuration of
Intermediate Physical Address size") removed the hardcoded setting
of VTCR_EL2.PS to use ID_AA64MMFR0_EL1.PARange instead, but didn't
remove the (now rather misleading) comment.
Fix the comments to match reality (at least for the next few minutes).
Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Diffstat (limited to 'arch/arm64')
| -rw-r--r-- | arch/arm64/include/asm/kvm_arm.h | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h index 94674eb..54bb4ba 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -129,6 +129,9 @@ * 40 bits wide (T0SZ = 24). Systems with a PARange smaller than 40 bits are * not known to exist and will break with this configuration. * + * VTCR_EL2.PS is extracted from ID_AA64MMFR0_EL1.PARange at boot time + * (see hyp-init.S). + * * Note that when using 4K pages, we concatenate two first level page tables * together. * @@ -138,7 +141,6 @@ #ifdef CONFIG_ARM64_64K_PAGES /* * Stage2 translation configuration: - * 40bits output (PS = 2) * 40bits input (T0SZ = 24) * 64kB pages (TG0 = 1) * 2 level page tables (SL = 1) @@ -150,7 +152,6 @@ #else /* * Stage2 translation configuration: - * 40bits output (PS = 2) * 40bits input (T0SZ = 24) * 4kB pages (TG0 = 0) * 3 level page tables (SL = 1) |
