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| author | Jingoo Han <jg1.han@samsung.com> | 2014-01-20 05:00:21 +0000 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2014-01-22 16:23:58 +0000 |
| commit | bd5f6dc304a054ccdc8dab43bef5e41d9a575b61 (patch) | |
| tree | 9ebc7702dc516cb52a8ec85ee5ae6ebb222cf021 /arch/arm64 | |
| parent | 883c057367014d20a14b5054e4eb0d81ce3bea5c (diff) | |
| download | op-kernel-dev-bd5f6dc304a054ccdc8dab43bef5e41d9a575b61.zip op-kernel-dev-bd5f6dc304a054ccdc8dab43bef5e41d9a575b61.tar.gz | |
arm64: mm: use ubfm for dcache_line_size
Use 'ubfm' for the bitfield move instruction; thus, single
instruction can be used instead of two instructions, when
getting the minimum D-cache line size from CTR_EL0 register.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64')
| -rw-r--r-- | arch/arm64/mm/proc-macros.S | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/arch/arm64/mm/proc-macros.S b/arch/arm64/mm/proc-macros.S index 8957b82..005d29e 100644 --- a/arch/arm64/mm/proc-macros.S +++ b/arch/arm64/mm/proc-macros.S @@ -38,8 +38,7 @@ */ .macro dcache_line_size, reg, tmp mrs \tmp, ctr_el0 // read CTR - lsr \tmp, \tmp, #16 - and \tmp, \tmp, #0xf // cache line size encoding + ubfm \tmp, \tmp, #16, #19 // cache line size encoding mov \reg, #4 // bytes per word lsl \reg, \reg, \tmp // actual cache line size .endm |
