diff options
author | David S. Miller <davem@davemloft.net> | 2016-08-30 00:54:02 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2016-08-30 00:54:02 -0400 |
commit | 6abdd5f5935fff978f950561f3c5175eb34dad73 (patch) | |
tree | 6f3ed3a4f4af9e74436ec9355ebf8201357f1c40 /arch/arm64/kvm/sys_regs.c | |
parent | 0b498a52778368ff501557d68c7b50878ab1701e (diff) | |
parent | e4e98c460ad38c78498622a164fd5ef09a2dc9cb (diff) | |
download | op-kernel-dev-6abdd5f5935fff978f950561f3c5175eb34dad73.zip op-kernel-dev-6abdd5f5935fff978f950561f3c5175eb34dad73.tar.gz |
Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
All three conflicts were cases of simple overlapping
changes.
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/arm64/kvm/sys_regs.c')
-rw-r--r-- | arch/arm64/kvm/sys_regs.c | 10 |
1 files changed, 1 insertions, 9 deletions
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index b0b225c..e51367d 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -823,14 +823,6 @@ static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, * Architected system registers. * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2 * - * We could trap ID_DFR0 and tell the guest we don't support performance - * monitoring. Unfortunately the patch to make the kernel check ID_DFR0 was - * NAKed, so it will read the PMCR anyway. - * - * Therefore we tell the guest we have 0 counters. Unfortunately, we - * must always support PMCCNTR (the cycle counter): we just RAZ/WI for - * all PM registers, which doesn't crash the guest kernel at least. - * * Debug handling: We do trap most, if not all debug related system * registers. The implementation is good enough to ensure that a guest * can use these with minimal performance degradation. The drawback is @@ -1360,7 +1352,7 @@ static const struct sys_reg_desc cp15_regs[] = { { Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, c10_AMAIR1 }, /* ICC_SRE */ - { Op1( 0), CRn(12), CRm(12), Op2( 5), trap_raz_wi }, + { Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre }, { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID }, |