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authorCatalin Marinas <catalin.marinas@arm.com>2013-04-24 14:47:02 +0100
committerCatalin Marinas <catalin.marinas@arm.com>2013-04-25 17:45:48 +0100
commit5108c67c376b3ee59cc7fbe46eaba481eb3419aa (patch)
tree0f2515769d1ceecc8f55380aff228c54929275e1 /arch/arm64/kernel
parent4b3ea2e04d2b8b37c5bc472f710d706b42e4fa06 (diff)
downloadop-kernel-dev-5108c67c376b3ee59cc7fbe46eaba481eb3419aa.zip
op-kernel-dev-5108c67c376b3ee59cc7fbe46eaba481eb3419aa.tar.gz
arm64: Execute DSB during thread switching for TLB/cache maintenance
The DSB following TLB or cache maintenance ops must be run on the same CPU. With kernel preemption enabled or for user-space cache maintenance this may not be the case. This patch adds an explicit DSB in the __switch_to() function. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/kernel')
-rw-r--r--arch/arm64/kernel/process.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c
index c2cc249..116a60a 100644
--- a/arch/arm64/kernel/process.c
+++ b/arch/arm64/kernel/process.c
@@ -313,6 +313,12 @@ struct task_struct *__switch_to(struct task_struct *prev,
hw_breakpoint_thread_switch(next);
contextidr_thread_switch(next);
+ /*
+ * Complete any pending TLB or cache maintenance on this CPU in case
+ * the thread migrates to a different CPU.
+ */
+ dsb();
+
/* the actual thread switch */
last = cpu_switch_to(prev, next);
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