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| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2015-03-17 10:55:12 +0100 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2015-03-19 19:46:02 +0000 |
| commit | da9c177de88679c2948dc9a5e2325b0dff4677b9 (patch) | |
| tree | 1ef1c5f3698aea6230899127fb1583ab55faa53c /arch/arm64/kernel/head.S | |
| parent | 6f4d57fa7021efbf135cfa068d56bc5035edffa1 (diff) | |
| download | op-kernel-dev-da9c177de88679c2948dc9a5e2325b0dff4677b9.zip op-kernel-dev-da9c177de88679c2948dc9a5e2325b0dff4677b9.tar.gz | |
arm64: enforce x1|x2|x3 == 0 upon kernel entry as per boot protocol
According to the arm64 boot protocol, registers x1 to x3 should be
zero upon kernel entry, and non-zero values are reserved for future
use. This future use is going to be problematic if we never enforce
the current rules, so start enforcing them now, by emitting a warning
if non-zero values are detected.
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm64/kernel/head.S')
| -rw-r--r-- | arch/arm64/kernel/head.S | 19 |
1 files changed, 18 insertions, 1 deletions
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index f5ac337..1fdf420 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -233,7 +233,7 @@ section_table: #endif ENTRY(stext) - mov x21, x0 // x21=FDT + bl preserve_boot_args bl el2_setup // Drop to EL1, w20=cpu_boot_mode adrp x24, __PHYS_OFFSET bl set_cpu_boot_mode_flag @@ -253,6 +253,23 @@ ENTRY(stext) ENDPROC(stext) /* + * Preserve the arguments passed by the bootloader in x0 .. x3 + */ +preserve_boot_args: + mov x21, x0 // x21=FDT + + adr_l x0, boot_args // record the contents of + stp x21, x1, [x0] // x0 .. x3 at kernel entry + stp x2, x3, [x0, #16] + + dmb sy // needed before dc ivac with + // MMU off + + add x1, x0, #0x20 // 4 x 8 bytes + b __inval_cache_range // tail call +ENDPROC(preserve_boot_args) + +/* * Determine validity of the x21 FDT pointer. * The dtb must be 8-byte aligned and live in the first 512M of memory. */ |
