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author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2014-08-08 12:51:39 +0100 |
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committer | Will Deacon <will.deacon@arm.com> | 2014-09-08 14:39:18 +0100 |
commit | 80c517b0ff71a4c874fed9196fd990d2d9e911f3 (patch) | |
tree | cd8df96023742759d214a0a2c1bc02680a2f35be /arch/arm64/kernel/cpuinfo.c | |
parent | 2ce7598c9a453e0acd0e07be7be3f5eb39608ebd (diff) | |
download | op-kernel-dev-80c517b0ff71a4c874fed9196fd990d2d9e911f3.zip op-kernel-dev-80c517b0ff71a4c874fed9196fd990d2d9e911f3.tar.gz |
arm64: add helper functions to read I-cache attributes
This adds helper functions and #defines to <asm/cachetype.h> to read the
line size and the number of sets from the level 1 instruction cache.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm64/kernel/cpuinfo.c')
-rw-r--r-- | arch/arm64/kernel/cpuinfo.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index 1771696..d8c5a59 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -20,8 +20,10 @@ #include <asm/cputype.h> #include <linux/bitops.h> +#include <linux/bug.h> #include <linux/init.h> #include <linux/kernel.h> +#include <linux/preempt.h> #include <linux/printk.h> #include <linux/smp.h> @@ -190,3 +192,15 @@ void __init cpuinfo_store_boot_cpu(void) boot_cpu_data = *info; } + +u64 __attribute_const__ icache_get_ccsidr(void) +{ + u64 ccsidr; + + WARN_ON(preemptible()); + + /* Select L1 I-cache and read its size ID register */ + asm("msr csselr_el1, %1; isb; mrs %0, ccsidr_el1" + : "=r"(ccsidr) : "r"(1L)); + return ccsidr; +} |