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author | Catalin Marinas <catalin.marinas@arm.com> | 2013-09-16 15:19:27 +0100 |
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committer | Catalin Marinas <catalin.marinas@arm.com> | 2014-05-09 15:47:49 +0100 |
commit | 15af1942dd61ee236a48b3de14d6f31c0b9e8116 (patch) | |
tree | d4f0163789eff325e8fd5088a70592abc3186c14 /arch/arm64/include | |
parent | 0e0276d1e1dd063cd14ce377707970d0417a0792 (diff) | |
download | op-kernel-dev-15af1942dd61ee236a48b3de14d6f31c0b9e8116.zip op-kernel-dev-15af1942dd61ee236a48b3de14d6f31c0b9e8116.tar.gz |
arm64: Expose ESR_EL1 information to user when SIGSEGV/SIGBUS
This information is useful for instruction emulators to detect
read/write and access size without having to decode the faulting
instruction. The current patch exports it via sigcontext (struct
esr_context) and is only valid for SIGSEGV and SIGBUS.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/include')
-rw-r--r-- | arch/arm64/include/uapi/asm/sigcontext.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm64/include/uapi/asm/sigcontext.h b/arch/arm64/include/uapi/asm/sigcontext.h index 690ad51..b72cf40 100644 --- a/arch/arm64/include/uapi/asm/sigcontext.h +++ b/arch/arm64/include/uapi/asm/sigcontext.h @@ -53,5 +53,12 @@ struct fpsimd_context { __uint128_t vregs[32]; }; +/* ESR_EL1 context */ +#define ESR_MAGIC 0x45535201 + +struct esr_context { + struct _aarch64_ctx head; + u64 esr; +}; #endif /* _UAPI__ASM_SIGCONTEXT_H */ |