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| author | Alim Akhtar <alim.akhtar@samsung.com> | 2016-11-12 15:47:12 +0530 |
|---|---|---|
| committer | Krzysztof Kozlowski <krzk@kernel.org> | 2016-11-15 20:11:48 +0200 |
| commit | eb708b0ff972bfe0e51c38fad6d517fae605ffa8 (patch) | |
| tree | 5b71a1f76a7bb67556c9f9484656a3a59388859d /arch/arm64/boot/dts | |
| parent | 8ac46fc57df82efbc19194dddd335b6c7a960c31 (diff) | |
| download | op-kernel-dev-eb708b0ff972bfe0e51c38fad6d517fae605ffa8.zip op-kernel-dev-eb708b0ff972bfe0e51c38fad6d517fae605ffa8.tar.gz | |
arm64: dts: Add ARM PMU node for exynos7
This patch adds ARM Performance Monitor Unit dt node for exynos7.
PMU provides various statistics on the operation of the CPU and
memory system at runtime, which are very useful when debugging or
profiling code. This enables the same.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
[krzk: Squashed with "Add level for cpu dt node for exynos7"]
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts')
| -rw-r--r-- | arch/arm64/boot/dts/exynos/exynos7.dtsi | 18 |
1 files changed, 14 insertions, 4 deletions
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi index 6328a66..d46ac94 100644 --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi @@ -35,28 +35,28 @@ #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu_atlas0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x0>; enable-method = "psci"; }; - cpu@1 { + cpu_atlas1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x1>; enable-method = "psci"; }; - cpu@2 { + cpu_atlas2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x2>; enable-method = "psci"; }; - cpu@3 { + cpu_atlas3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x3>; @@ -472,6 +472,16 @@ status = "disabled"; }; + arm-pmu { + compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3"; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu_atlas0>, <&cpu_atlas1>, + <&cpu_atlas2>, <&cpu_atlas3>; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 |
