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| author | Ben Dooks <ben-linux@fluff.org> | 2010-01-20 11:09:28 +0900 |
|---|---|---|
| committer | Ben Dooks <ben-linux@fluff.org> | 2010-01-21 13:45:51 +0900 |
| commit | 6890556c140469622497bea98cf49bf93f92f922 (patch) | |
| tree | 67bf70c1bc46e02b77f2be9e659bff57bc2e844f /arch/arm/plat-samsung/include/plat/regs-watchdog.h | |
| parent | 54b89177ac533dc7439491afd26baf59464b425c (diff) | |
| download | op-kernel-dev-6890556c140469622497bea98cf49bf93f92f922.zip op-kernel-dev-6890556c140469622497bea98cf49bf93f92f922.tar.gz | |
ARM: SAMSUNG: Move more support into plat-samsung
Move header files which are not likely to be touched in
any further support addition out of plat-s3c's include
directory into plat-samsung.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm/plat-samsung/include/plat/regs-watchdog.h')
| -rw-r--r-- | arch/arm/plat-samsung/include/plat/regs-watchdog.h | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/arch/arm/plat-samsung/include/plat/regs-watchdog.h b/arch/arm/plat-samsung/include/plat/regs-watchdog.h new file mode 100644 index 0000000..4938492 --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/regs-watchdog.h @@ -0,0 +1,41 @@ +/* arch/arm/mach-s3c2410/include/mach/regs-watchdog.h + * + * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> + * http://www.simtec.co.uk/products/SWLINUX/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * S3C2410 Watchdog timer control +*/ + + +#ifndef __ASM_ARCH_REGS_WATCHDOG_H +#define __ASM_ARCH_REGS_WATCHDOG_H + +#define S3C_WDOGREG(x) ((x) + S3C_VA_WATCHDOG) + +#define S3C2410_WTCON S3C_WDOGREG(0x00) +#define S3C2410_WTDAT S3C_WDOGREG(0x04) +#define S3C2410_WTCNT S3C_WDOGREG(0x08) + +/* the watchdog can either generate a reset pulse, or an + * interrupt. + */ + +#define S3C2410_WTCON_RSTEN (0x01) +#define S3C2410_WTCON_INTEN (1<<2) +#define S3C2410_WTCON_ENABLE (1<<5) + +#define S3C2410_WTCON_DIV16 (0<<3) +#define S3C2410_WTCON_DIV32 (1<<3) +#define S3C2410_WTCON_DIV64 (2<<3) +#define S3C2410_WTCON_DIV128 (3<<3) + +#define S3C2410_WTCON_PRESCALE(x) ((x) << 8) +#define S3C2410_WTCON_PRESCALE_MASK (0xff00) + +#endif /* __ASM_ARCH_REGS_WATCHDOG_H */ + + |
