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authorKukjin Kim <kgene.kim@samsung.com>2012-01-22 21:46:13 +0900
committerKukjin Kim <kgene.kim@samsung.com>2012-03-14 02:13:03 -0700
commit87b3c6ef1d7eb24c63cc3c7b7a424178aef410fc (patch)
treead925e2348684def8ef63be8bd45be9b43554b8c /arch/arm/plat-s5p/clock.c
parent920f4880162e70cb4fc8db8e7b0f15f3b307baf9 (diff)
downloadop-kernel-dev-87b3c6ef1d7eb24c63cc3c7b7a424178aef410fc.zip
op-kernel-dev-87b3c6ef1d7eb24c63cc3c7b7a424178aef410fc.tar.gz
ARM: EXYNOS: add clock part for EXYNOS5250 SoC
This patch adds clock-exynos5.c for EXYNOS5250 now and that can be used for other EXYNOS5 SoCs later. Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/plat-s5p/clock.c')
-rw-r--r--arch/arm/plat-s5p/clock.c36
1 files changed, 36 insertions, 0 deletions
diff --git a/arch/arm/plat-s5p/clock.c b/arch/arm/plat-s5p/clock.c
index 963edea..f68a9bb 100644
--- a/arch/arm/plat-s5p/clock.c
+++ b/arch/arm/plat-s5p/clock.c
@@ -61,6 +61,20 @@ struct clk clk_fout_apll = {
.id = -1,
};
+/* BPLL clock output */
+
+struct clk clk_fout_bpll = {
+ .name = "fout_bpll",
+ .id = -1,
+};
+
+/* CPLL clock output */
+
+struct clk clk_fout_cpll = {
+ .name = "fout_cpll",
+ .id = -1,
+};
+
/* MPLL clock output
* No need .ctrlbit, this is always on
*/
@@ -101,6 +115,28 @@ struct clksrc_sources clk_src_apll = {
.nr_sources = ARRAY_SIZE(clk_src_apll_list),
};
+/* Possible clock sources for BPLL Mux */
+static struct clk *clk_src_bpll_list[] = {
+ [0] = &clk_fin_bpll,
+ [1] = &clk_fout_bpll,
+};
+
+struct clksrc_sources clk_src_bpll = {
+ .sources = clk_src_bpll_list,
+ .nr_sources = ARRAY_SIZE(clk_src_bpll_list),
+};
+
+/* Possible clock sources for CPLL Mux */
+static struct clk *clk_src_cpll_list[] = {
+ [0] = &clk_fin_cpll,
+ [1] = &clk_fout_cpll,
+};
+
+struct clksrc_sources clk_src_cpll = {
+ .sources = clk_src_cpll_list,
+ .nr_sources = ARRAY_SIZE(clk_src_cpll_list),
+};
+
/* Possible clock sources for MPLL Mux */
static struct clk *clk_src_mpll_list[] = {
[0] = &clk_fin_mpll,
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